Faster-Than-At-Speed Test Considering IR-drop Effects

Interconnect defects such as weak resistive opens, shorts and bridges increases the path delay affected by a pattern during manufacturing test but not significant enough to cause a failure at functional frequency. Faster-than-at-speed tests have been proposed to detect such small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exacerbate the already well known issue of IR-drop during test. This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. Although, it may be argued that such false failures can be easily identified by applying the faster-than-at-speed test pattern to a larger sample of good chips. A trivial solution to determine the maximum test frequency that a pattern can be applied would be to iteratively increase the applied frequency of the pattern on the tester until a good chip starts to fail. However, considering the test time impact and analysis required for a large test pattern set makes such a solution impractical. Also, it is impossible to apply each test pattern at an individual frequency either due to hardware limitations of the automatic test equipment (ATE) to generate higher frequencies or due to long synchronization times of on-chip clock generators (phase locked loops (PLLs)) affecting test time.


Test Pattern Transition Fault Path Delay Switching Activity Clock Period 
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