As technology scales, new subtle defects are seen during fabrication which can have significant impacts on yield and reliability of the shipped products. Resistive open and short are two such defects that cause timing or logic failures in the design. Such defects can cause gross or small delay defects depending on the size of their resistance. It is proven that the population of such defects increases as technology scales, thus increasing small delay defects.
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References
1. X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design & Test of Computers, pp. 17-25, Sep-Oct 2003.
2. V. Jayaram, J. Saxena and K. Butler, Scan-Based Transition-Fault Test Can Do Job, EE Times, Oct. 2003.
K. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1971–1983, Dec. 1993.
4. T. M. Mak, A. Krstic, K. Cheng and L. Wang, “New challenges in delay testing of nanometer, multigigahertz designs,” IEEE Design & Test of Computers, pp. 241-248, May-Jun 2004.
5. M. Bushnell and V. Agrawal, Essentials of Electronics Testing, Kluwer Publishers, 2000.
6. Cadence Inc., “http://www.cadence.com,”, 2005.
7. Synopsys Inc., “User Manuals for SYNOPSYS Toolset Version 2004.06,” Synopsys, Inc., 2004.
8. H. Hao and E.J. McCluskey, “Very-low-voltage testing for weak CMOS logic ICs,” in Proc. Int. Test Con. (ITC’93), pp. 275-284, 1993.
R. Foster, “Why Consider Screening, Burn-In, and 100-Percent Testing for Commercial Devices?,” IEEE Transactions on Manufacturing Technology, vol. 5, no. 3, pp. 52–58, 1976.
10. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” in Proc. Design Automation Conference (DAC06), 2006
11. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects,” in Proc. Int. Conf. on Computer-Aided Design (ICCAD’06), 2006.
12. X. Lin, et. al, “Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects,” in Proc. IEEE Asian Test Symposium (ATS’06), 2006.
13. S. Kundu, P. Engelke, I. Polian and B. Baker, “On detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing,” to appear in IEEE Asian Test Symp. (ATS’05), 2005.
14. P. Gupta and M. S. Hsiao, “ALAPTF: A new transition fault model and the ATPG algorithm,” in Proc. Int. Test Conf. (ITC’04), pp. 1053-1060, 2004.
A. K. Majhi, V. D. Agrawal, J. Jacob, L. M. Patnaik, “Line coverage of path delay faults,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 610–614, 2000.
16. W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balichandran, “K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits,” in Proc. Int. Test Conf. (ITC’04), pp. 223-231, 2004.
17. B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” in Proc. Int. Test Conf. (ITC’04), pp. 213-222, 2004.
18. J. Saxena, K. M. Butler, V. B. Jayaram, N. V. Arvind, P. Sreeprakash and M. Hachingerr, “A Case Study of IR-Drop in Structured At-Speed Testing,” in Proc. Int. Test Conf. (ITC’03), pp. 1098-1104, 2003.
19. J. Rearick and R. Rodgers, “Calibrating Clock Stretch During AC Scan Testing,” in Proc. Int. Test Conf. (ITC’05), 2005.
20. B. Benware, C. Schuermyer, N. Tamarapalli, Kun-Han Tsai, S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy, “Impact of multiple-detect test patterns on product quality,” in Proc. Int. Test Conf. (ITC’03), pp. 1031-1040, 2003.
21. B.N. Lee, L. C. Wang and M. S. Abadir, “Reducing pattern delay variations for screening frequency dependent defects,” in Proc. VLSI Test Symp. (VTS’05), pp. 153-160, 2005.
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(2008). Screening Small Delay Defects. In: Nanometer Technology Designs High-Quality Delay Tests. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-75728-5_7
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