Modern Very Large Scale Integration (VLSI) designs require extensive testing to ensure the shipped product will function correctly when it reaches the consumer. Transition delay fault testing is one of many commonly used testing techniques. However, it is a structural-based test and the chip may suffer from overtesting. A simple method to avoid overtesting is to identify the faults that are functionally untestable and omit the faults from the fault list but automatic test pattern generation (ATPG) tool may incidentally detect these faults when filling in don't-care states. The percentage of don't-care bits in a test pattern can be very high in large designs, about 99%. These don't-care bits are either filled randomly to provide higher defect coverage by increasing the chance of detecting non-modeled faults or filled by compression tools to obtain the highest compression to reduce test data volume and test time. However, filling these don't-care bits without considering the functionally untestable faults can cause yield loss.
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(2008). Avoiding Functionally Untestable Faults. In: Nanometer Technology Designs High-Quality Delay Tests. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-75728-5_6
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