Local At-Speed Scan Enable Generation Using Low-Cost Testers

At-speed testing is becoming crucial for modern VLSI systems which operate at clock speeds of hundreds of megahertz to several gigahertz. In a scan-based test methodology, it is common to use transition delay fault model for at-speed testing. The test procedure is to create a transition at a node using scan chains for controllability, capture the results after a time period equal to one system clock cycle, and observe the contents of the scan chain through serial shift operation. The launching of the transition can be done either in the last cycle of scan shift (called launch-off-shift), or in a functional launch cycle that follows the scan shift and precedes the fast capture (called launch-off-capture).When comparing these two, the launch-off-shift technique offers significant advantages over the launch-off-capture in terms of coverage and pattern count, but since it requires the scan enable signal to change state in the time period of one functional clock cycle, considerable engineering resources and design efforts are required to close the timing on the scan enable signal. Usually, due to high-speed pin limitation, low-cost testers may not be able to provide the at-speed scan enable signal as required by launch-off-shift technique.