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At-speed Test Challenges for Nanometer Technology Designs

As the electronic design automation (EDA) industry focuses on design-for-manufacturability (DFM), the older problem of design-for-test has almost been forgotten. But ICs built at 90 nanometers and below pose new and com-plex challenges for design-for-testability (DFT) tools and techniques. At those geometries, small delay defects become a major contributor to chip failures, but they can't be detected by conventional automatic test pattern generation (ATPG) tools since they are timing unaware. Low-power ICs, which will in-clude most chips at 65nm technology node, demand new approaches to low power scan design and pattern generation. Test data run over many dice and wafers can provide valuable diagnostic information that helps foundries and designers ramp up their yields. In this sense, DFT meets DFM and becomes a critical element in the attempt to mitigate process variability.

Keywords

Critical Path Transition Fault Delay Test Delay Defect Automatic Test Pattern Generation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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