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Testing SoC Interconnects for Signal Integrity

As the technology shrinks and working frequency is already in multi gigahertz range, design and test of interconnects are no longer trivial issues. Stuck-at fault model can detect bridge and open faults. But, transient, timing, and noise related faults cannot be detected using traditional stuck-at and delay test patterns. New design-for-test (DFT) methods and pattern generation algorithms are required to effectively consider such faults in high-speed designs. The issues related to interconnect design and test will soon become dominant as technology scales going into sub-50nm. Specifically, various issues of signal integrity loss including detection and diagnosis are becoming a great challenge.

Keywords

Test Pattern Multiple Transition Signal Integrity Very Large Scale Integration Automatic Test Equipment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer Science+Business Media, LLC 2008

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