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Delay Fault Testing in Presence of Maximum Crosstalk

High speed interconnects have been contributing to a majority of the delay present in modern sub-micron technologies. As the trend towards nanoscale continues, the effects from this delay will only worsen. Although it is possible to compensate for this with design tools, the limitations of testing tools are beginning to surface since parasitic coupling capacitance is not directly addressed by testing tools. A chip passing a manufacturing test with a specific pattern set only suggests that it will pass under the specific operating and stimulus conditions in which the patterns were applied on the tester. However, in the field, the surrounding paths around the critical paths may experience significantly different switching activity causing it to fail in the field. This chapter presents a structural test pattern generation procedure that magnifies the effect of parasitic crosstalk effects on critical paths. The pattern generation procedure considers the physical design and transition direction without simulation to increase the delay on the critical path. This work intends to minimize the escape ratio and improve in the field reliability. There are few modern testing tools that account for timing, but these products are not fully aware of the timing violations that may occur due to signal integrity degradation in modern technologies. This leads to silicon failures and escape.

Keywords

Critical Path Coupling Capacitance Delay Fault Fault List Automatic Test Pattern Generation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer Science+Business Media, LLC 2008

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