Pattern Generation for Power Supply Noise Analysis

This chapter presents an automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. This information can benefit both the design and failure anaysis teams. The generated test patterns can also be used for targeting supply noise effects during fabrication test. The design team can use this information to further analyze the power/ground network for driving maximum current to the circuit without affecting the circuit performance.


Current Waveform Switching Activity Benchmark Circuit Automatic Test Pattern Generation Pattern Pair 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media, LLC 2008

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