Partitioning Strategy for Embedded Multiprocessor FPGA Systems

  • Trong-Yen Lee
  • Yang-Hsin Fan
  • Yu-Min Cheng
  • Chia-Chun Tsai
  • Rong-Shue Hsiao
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 6)

Nanometer technology is gradually being applied after deep submicron technology due to the rapid progress of the VLSI fabrication process. Recently, system- on-a-chip (SoC) based products are gaining more advantages such as lower cost and power and high performance, but the new challenges are spending effort on hardware–software codesign, co-verification, and reusable intelligent property (IP). Moreover, the new fabrication process enhances transistor capacity greatly so that built-in multiprocessor system-on-a-chips (MPSoC) such as Xilinx [1] Virtex series FPGA platform are possible. Unfortunately, SoC's challenges are not solved completely; the MPSoC era is coming. Why is technology moving toward MPSoC? The reason is that the characteristic of MPSoC is simpler and more flexible than other architectures. For example, MPSoC-based architecture is easier for floating-pointoperation than redesigned hardware architecture. For computing mass and complex data, MPSoC is made more flexible by running software in parallel as opposed to hardware.


Genetic Algorithm Execution Time Constraint Satisfaction Problem Memory Size System Element 
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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Trong-Yen Lee
    • 1
  • Yang-Hsin Fan
    • 1
    • 2
  • Yu-Min Cheng
    • 3
  • Chia-Chun Tsai
    • 4
  • Rong-Shue Hsiao
    • 1
  1. 1.Department of Electronic Engineering, Institute of Computer and Communication EngineeringNational Taipei University of TechnologyTaipeiRepublic of China
  2. 2.Information System Section of LibraryNational Taitung UniversityTaitungRepublic of China
  3. 3.Chroma CorporationRepublic of China
  4. 4.Department of Computer Science and Information EngineeringNanhua UniversityChia-YiRepublic of China

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