A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs
This paper describes the design of a high-speed CMOS sample and- hold (S/H) circuit for pipelined analog-to-digital converters (ADCs). This S/H circuit consists of a switched-capacitor (SC) amplifier and a comparator to generate the mixed-mode sampled output data, which are represented both in analog and digital forms. The mixed-mode sampling technique reduces the operational amplifier (op amp) output swing. As a result, the requirements on op amp DC gain, slew rate and bandwidth are relaxed; the linearity of the SC amplifier is also improved. The reduction of signal swing in the front-end also brings benefit to the pipelined stages in speed and power consumption. The aperture errors at high frequency are minimized by time constant matching and digital error correction logic in the pipelined ADC. Designed in a 0.18-µm CMOS process, the proposed S/H circuit operates up to 200-MSample/s with a total harmonic distortion (THD) less than -60 dB and a signal-to-noise and distortion ratio (SNDR) larger than 59 dB in the worst-case simulation. The power consumption of the mixed-mode S/H circuit is 3.6-mW with 1.8-V supply voltage.
KeywordsTotal Harmonic Distortion Slew Rate Pipeline Stage Gain Error Output Swing
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