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Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation

  • Tsuyoshi Iwagaki
  • Satoshi Ohtake
  • Hideo Fujiwara
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 249)

This paper presents a method of broadside transition test generation for partial scan circuits. The proposed method first transforms the kernel circuit of a given partial scan circuit into some combinational circuits. Then, by performing stuck-at test generation on the transformed circuits, broadside transition tests for the original circuit are obtained. This method allows us to use existing stuck-at test generation tools in order to generate broadside transition tests. It is shown that the proposed scheme is effective in area overhead and test generation time by experiments. In this paper, some variations of broadside transition testing of partial scan circuits are also discussed in terms of different test application strategies and fault sizes.

Keywords

Transition Fault Test Frame Area Overhead Sequential Circuit Combinational Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© International Federation for Information Processin 2008

Authors and Affiliations

  • Tsuyoshi Iwagaki
    • 1
  • Satoshi Ohtake
    • 2
  • Hideo Fujiwara
    • 2
  1. 1.School of Information ScienceJapan Advanced Institute of Science and TechnologyNomiJapan
  2. 2.Graduate School of Information ScienceNara Institute of Science and TechnologyJapan

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