A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits

  • Renato Hentschke
  • Sandro Sawicki
  • Marcelo Johann
  • Ricardo Reis
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 249)

This paper presents an algorithm for I/O pins partitioning and placement targeting 3D circuits. The method starts from a standard 2D placement of the pins around a flat rectangle and outputs a 3D representation of the circuit composed of a set of tiers and pins placed at the four sides of the resulting cube. The proposed algorithm targets a balanced distribution of the I/Os that is required both for accommodating the pins evenly as well as to serve as an starting point for cell placement algorithms that are initially guided by I/O's locations, such as analytical placers. Moreover, the I/O partitioning tries to set pins in such a way the it allows the cell placer to reach a reduced number of 3D-Vias. The method works in two phases: first the I/O partitioning considering the logic distances as weights; second, fix the I/Os and perform partitioning of the cells. The experimental results show the effectiveness of the approach on balance and number of 3D-Vias compared to simplistic methods for I/O partitioning, including traditional min-cut algorithms. Since our method contains the information of the whole circuit compressed in a small graph, it could actually improve the partitioning algorithm at the expense of more CPU time. Additional experiments demonstrated that the method could be adapted to further reduce the number of 3D-Vias if the I/O pin balance constraint can be relaxed.


Metal Layer Research Trend Very Large Scale Integration Wire Length Placement Algorithm 


  1. [1]
    Ispd04 - ibm standard cell benckmarks with pads., 2006.Google Scholar
  2. [2]
    C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S. Sapatnekar. Placement and routing in 3d integrated circuits. Design and Test of Computers, pages 520-531, Nov-Dec 2005.Google Scholar
  3. [3]
    C. Ababei, H. Mogal, and K. Bazargan. Three-dimensional place and route for fpgas. In ASP-DAC ’05: Proceedings of the 2003 conference on Asia South Pacific design automation. IEEE Press, 2005.Google Scholar
  4. [4]
    C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan. Quadratic placement revisited. In DAC ’97: Proceedings of the 34th annual conference on Design automation, pages 752-757, New York, NY, USA, 1997. ACM Press.CrossRefGoogle Scholar
  5. [5]
    K. Banerjee, S. Souri, P. Kapur, and K. Saraswat. 3d-ics: A novel chip design for improving deep submicrometer interconnect performance and systems on-chip integration. Proceedings of IEEE, 89:602-633, 2001.CrossRefGoogle Scholar
  6. [6]
    A. E. Caldwell, A. B. Kahng, and I. L. Markov. Can recursive bisection alone produce routable placements? In DAC ’00: Proceedings of the 37th conference on Design automation, pages 477-482, New York, NY, USA, 2000. ACM Press.CrossRefGoogle Scholar
  7. [7]
    S. Das, A. Chandrakasan, and R. Reif. Design tools for 3-d integrated circuits. In ASPDAC: Proceedings of the 2003 conference on Asia South Pacific design automation, pages 53-56, New York, NY, USA, 2003. ACM Press.Google Scholar
  8. [8]
    S. Das, A. Chandrakasan, and R. Reif. Calibration of rent’s rule models for three-dimensional integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12:359-366, 2004.CrossRefGoogle Scholar
  9. [9]
    S. Das, A. Fan, K.-N. Chen, C. S. Tan, N. Checka, and R. Reif. Technology, performance, and computer-aided design of three-dimensional integrated circuits. In ISPD ’04: Proceedings of the 2004 international symposium on Physical design, pages 108-115, New York, NY, USA, 2004. ACM Press.CrossRefGoogle Scholar
  10. [10]
    W. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. Sule, M. Steer, and P. Franzon. Demystifying 3d ics: The pros and cons of going vertical. Design and Test of Computers, pages 498-510, Nov-Dec 2005.Google Scholar
  11. [11]
    Y. Deng and W. P. Maly. Interconnect characteristics of 2.5-d system inte-gration scheme. In ISPD ’01: Proceedings of the 2001 international sympo-sium on Physical design, pages 171-175, New York, NY, USA, 2001. ACM Press.CrossRefGoogle Scholar
  12. [12]
    B. Goplen and S. Sapatnekar. Efficient thermal placement of standard cells in 3d ics using a force directed approach. In ICCAD ’03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, page 86, Washington, DC, USA, 2003. IEEE Computer Society.Google Scholar
  13. [13]
    S. Gupta, M. Hilbert, S. Hong, and R. Patti. Techniques for pro- ducing3d ics with high-density interconnect,2005.Available at: ¡http://www.tezzaron.com/¿. Access on: Aug. 2005.
  14. [14]
    G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Applications in vlsi domain. IEEE Transactions on Very Large Integration (VLSI) Systems, 7:69-79, March 1999.CrossRefGoogle Scholar
  15. [15]
    I. Kaya, S. Salewski, M. Olbrich, and E. Barke. Wirelength reduction us- ing 3-d physical design. In Integrated Circuit and System Design - Power and Timing Modeling, Optimization and Simulation; Proceedings of 14th International Workshop, PATMOS 2004, 2004.Google Scholar
  16. [16]
    G. Liu, Z. Li, Q. Zhou, X. Hong, and H. H. Yang. 3d placement algorithm considering vertical channels and guided by 2d placement solution. In ASI-CON 2005: 6th International Conference On ASIC, pages 24-27, 2005.Google Scholar
  17. [17]
    S. Obenaus and T. Szymanski. Gravity: Fast placement for 3-d vlsi. ACM Transacions on Design Automation of Electronic Systems, 8:69-79, March 1999.Google Scholar
  18. [18]
    R. Patti. Three-dimensional integrated circuits and the future of system- on-chip designs. Proceedings of IEEE, 94:1214-1224, 2006.CrossRefGoogle Scholar
  19. [19]
    A. Rahman and R. Reif. System-level performance evaluation of three- dimensional integrated circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8, December 2000.Google Scholar
  20. [20]
    A. Rahman and R. Reif. Thermal analysis of three-dimensional (3-d) inte- grated circuits (ics). In Proceedings of the IEEE 2001 International Interconnect Technology Conference, pages 157-159, 2001.Google Scholar
  21. [21]
    N. Viswanathan, M. Pan, and C. C.-N. Chu. Fastplace: an analytical placer for mixed-mode designs. In: ISPD ’05: Proceedings of the 2005 international symposium on physical design, pages 221-223, New York, NY, USA, 2005. ACM Press.CrossRefGoogle Scholar

Copyright information

© International Federation for Information Processin 2008

Authors and Affiliations

  • Renato Hentschke
    • 1
  • Sandro Sawicki
    • 2
  • Marcelo Johann
    • 1
  • Ricardo Reis
    • 1
  1. 1.Instituto de InformaticaUniversidade Federal do Rio Grande do SulBrazil
  2. 2.Universidade Reg. do Noroeste do Estado do RSBrazil

Personalised recommendations