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Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation

  • Zeynep Toprak Deniz
  • Yusuf Leblebici
  • Eric Vittoz
Conference paper
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 249)

This work presents the design of an on-line energy optimizer unit, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements (PE), tailored to the instantaneous workload information and is fully adaptive to variations in process and temperature. The circuit design borrows some of the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple cores. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law (KCL) constraints in an equivalent resistive network is exploited. To our best knowledge, this is the first study of its kind to demonstrate an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements.

Keywords

Supply Voltage Processing Element Task Graph Resistive Network Task Duration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    M. Sirvastava, “Power-aware design energy consumers & sources, reduction & management.” UCLA, EE202A Fall 2002 Lecture notes, 7 and 8, 2002, University of California, LA.Google Scholar
  2. [2]
    A. Chandrakasan, R. Min, and M. Bhardwaj, “Power aware wireless microsensor systems,” in Proceedings of the 28th European Solid-State Circuits Conference, p. In Keynote Paper, 2002.Google Scholar
  3. [3]
    D. M. Monticelli, “Taking a system approach to energy management,” in Pro-ceedings of the 29th European Solid-State Circuits Conference, vol. 1, (Estoril, Portugal), pp. 15-19, Sep. 2003.Google Scholar
  4. [4]
    A. Chandrakasan, V. Gutnik, and T. Xanthopoulos, “Data driven signal process-ing: an approach for energy efficient computing,” in Proceedings of the Interna-tional Symposium on Low Power Electronics and Design, (Monterey, California, United States), pp. 347-352, IEEE Press, 1996.CrossRefGoogle Scholar
  5. [5]
    K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, T. Maeda, Y. Watan-abe, K. Matsuda, T. Kuroda, and T. Sakurai, “A 300 MIPS/W RISC core proces-sor with variable supply-voltage scheme in variable threshold-voltage CMOS,” in Proceedings of IEEE Custom Integrated Circuits Conference, pp. 587-590, May 1997.Google Scholar
  6. [6]
    K. Usami, M. Igarashi, T. Ishikawa, M. Kanazawa, M. Takahashi, M. Hamada, H. Arakida, T. Terazawa, and T. Kuroda, “Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques,” in Proceedings of the 35th Design Automation Conference, (San Francisco, CA), pp. 483-488, June 1998.Google Scholar
  7. [7]
    K. Flautner, D. Flynn, and M. Rives, “A combined hardware-software approach for low-power SoCs: Applying adaptive voltage scaling and intelligent energy man-agement software,” in Proceedings of System-on-Chip and ASIC Design Confer-ence, DesignCon, Jan. 2003.Google Scholar
  8. [8]
    C. Poirier, R. McGowen, C. Bostak, and S. Naffziger, “Power and temperature control on a 90nm Itanium -Family Processor,” in Proceedings of IEEE Interna- tional Solid-State Circuits Conference, Digest of Technical Paper, vol. 2, pp. 304-305, Feb. 2005.Google Scholar
  9. [9]
    X. Fan, C. S. Ellis, and A. R. Lebeck, “The synergy between power-aware memory systems and processor voltage scaling,” in Power-Aware Computer Systems, 3rd International Workshop, pp. 164-179, Dec. 2003.Google Scholar
  10. [10]
    D. B. Kirk, Accurate and Precise Computation using Analog VLSI, with Applica- tions to Computer Graphics and Neural Networks. PhD thesis, California Institute of Technology, Pasadena, California, March 1993.Google Scholar
  11. [11]
    G. Cauwenberghs, “A fast stochastic error-decent algorithm for supervised learn- ing and optimization,” in Advances in Neural Information Processing Systems, vol. 5, pp. 244-251, 1993.Google Scholar
  12. [12]
    L. O. Chua and L. Gui-Nian, “Nonlinear programming without computation,” in IEEE Transactions on Circuits and Systems II, vol. CAS-31, pp. 182-188, Feb. 1984.Google Scholar
  13. [13]
    A. Dembo and T. Kailath, “Model free distributed learning,” in IEEE Transac- tions on Neural Networks, vol. 1, pp. 58-70, 1990.CrossRefGoogle Scholar
  14. [14]
    R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Process- ing. New York: John Wiley and Sons, 1986.Google Scholar
  15. [15]
    Technical Report, Transmeta Corporation, http://www.transmeta.com.
  16. [16]
    S. Lee and T. Sakurai, “Run-time power control scheme using software feedback loop for low-power real-time application,” in Proceedings of the Asia and South Pacific Design Automation Conference, (Yokohama, Japan), pp. 381-386, Jan. 2000.Google Scholar
  17. [17]
    S. Lee and T. Sakurai, “Run-time voltage hopping for low-power real-time sys- tems,” in Proceedings of the 37th Design Automation Conference, (Los Angeles, California, United States), pp. 806-809, June 2000.Google Scholar
  18. [18]
    A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. M. Al-Hashimi, “Overhead- conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems,” in Proceedings of the Design, Automation and Test in Eu-rope Conference and Exhibition, (Paris, France), pp. 105-118, Feb. 2004.Google Scholar
  19. [19]
    B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, “Theoretical and practical limits of dynamic voltage scaling,” in Proceedings of the 41st Design Automation Conference, (San Diego, CA, USA), pp. 868-873, 2004.Google Scholar
  20. [20]
    S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads,” in Proceedings of the International Conference on Computer Aided Design, (San Jose, California), pp. 721-725, Nov. 2002.Google Scholar
  21. [21]
    J. Liu, P. H. Chou, and N. Bagherzadeh, “Communication speed selection for embedded systems with networked voltage-scalable processors,” in Proceedings of the 10th International Workshop on Hardware/Software Codesign, (Estes Park, Colorado), pp. 169-174, May 2002.Google Scholar
  22. [22]
    Y. Zhang, X. Hu, and D. Chen, “Task scheduling and voltage selection for energy minimization,” in Proceedings of the 39th Design Automation Conference, (New Orleans, LA, USA), pp. 183-188, June 2002.Google Scholar
  23. [23]
    E. A. Vittoz, “Pseudo-resistive networks and their applications to analog collective computation,” in Proceedings of the 7th International Conference on Artificial Neural Networks, (Lausanne, Switzerland), pp. 1133-1150, Oct. 1997.Google Scholar
  24. [24]
    J. C. Maxwell, A Treatise in Electricity and Magnetism, vol. 1. New York, USA: Dover Publications, Inc., third ed., 1954.Google Scholar
  25. [25]
    E. Vittoz, “Analog VLSI for collective computation,” in Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, vol. 2, pp. 3-6, Sep. 1998.Google Scholar
  26. [26]
    Z. T. Deniz, Y. Leblebici, and E. Vittoz, “Configurable on-line global energy optimization in multi-core embedded systems using principles of analog computation,” in Proceedings of 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 379-384, Oct. 2006.Google Scholar
  27. [27]
    Z. T. Deniz, Multi-Unit Global Energy Management and Optimization for Network-on-Chip Applications. PhD thesis, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, February 2006.Google Scholar
  28. [28]
    Z. T. Deniz, Y. Leblebici, and E. Vittoz, “On-line global energy optimization in multi-core systems using principles of analog computation,” IEEE Journal of Solid-State Circuits, accepted for publication in July 2007 issue.Google Scholar

Copyright information

© International Federation for Information Processin 2008

Authors and Affiliations

  • Zeynep Toprak Deniz
    • 1
  • Yusuf Leblebici
    • 1
  • Eric Vittoz
    • 1
  1. 1.Ecole Polytechnique Fédérale de LausanneSwitzerland

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