Reversible and Testable Circuits for Molecular QCA Design

  • X. Ma
  • J. Huang
  • C. Metra
  • F. Lombardi
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

Emerging technologies have been widely advocated to supersede the projected limitations of CMOS at the end of the roadmap [27]. Computation at nano regimes is substantially different from conventional VLSI. Extremely small feature size, high device density and low power are some of the attributes that emerging technologies must address, while implementing new computational paradigms [1]. One of these paradigm is reversible computing. Reversible computation is accomplished by establishing a one-to-one onto mapping between the input states and output states of the circuit [7]. This bijective property was initially investigated by Landauer who showed that kT ln 2 joules of energy are generated for each bit of information lost due to non reversible computation [6]. But,if computation is performed in a reversible manner, it has been shown that kT In 2 energy dissipation would not necessarily occur. Due to the bijective property, testing of reversible logic is generally simpler than conventional irreversible logic [31].


Majority Voter Reversible Logic Fault Pattern CNOT Gate Reversible Gate 
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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • X. Ma
    • 1
  • J. Huang
    • 1
  • C. Metra
    • 2
  • F. Lombardi
    • 3
  1. 1.Department of Electrical and Computer EngineeringNortheastern UniversityBoston
  2. 2.Department of Electrical EngineeringUniversity of BolognaBolognaItaly
  3. 3.Department of Electrical and Computer EngineeringNortheastern UniversityBostonUSA

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