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Defect Tolerance in Crossbar Array Nano-Architectures

  • M. B. Tahoori
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

Conventional lithography-based CMOS technology down-scaling faces serious challenges at both the device and system levels. Some of the challenges at the device level are manufacturing variability, sub-threshold leakage, power dissipation, increased circuit noise sensitivity, and cost/performance improvement. At the system level, some of the challenges are effective utilization of over-a-billion gates, system integration issues, power, and performance. While temporary solutions to these challenges will continue to be found, alternative devices need to be explored for possible replacement of or integration within CMOS. Some of the emerging candidates include carbon nanotubes (CNTs) [1–3], silicon nanowires (NWs)[4,5], resonant tunneling diodes (RTDs) [6], single electron transistors [7],and quantum-dot cellular automata (QCA)[8].

Keywords

Bipartite Graph Greedy Algorithm Defect Density Physical Design Defect Injection 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • M. B. Tahoori
    • 1
  1. 1.Northeastern UniversityBoston

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