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Test and Defect Tolerance for Reconfigurable Nanoscale Devices

  • M. Tehranipoor
  • R. Rad
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

According to international technology roadmap for semiconductors (ITRS) [1] scaling of CMOS technology will face many practical and theoretical difficulties within the next few years. In order to enhance the domain of information processing applications beyond CMOS capabilities and continue Moore's law, several technologies are being examined for future computing devices. Among these technologies, quantum devices, optical devices, biologically inspired devices, molecular devices, nanowire and carbon nanotube based devices are under intense investigation. High defect rate is expected to be the common problem for all these emerging technologies. Defect density of such technologies will be considerably higher than that of CMOS due to indeterministic fabrication processes and dominance of quantum effects at such scale. Dealing with such high defect densities requires wide research on new test and defect tolerance techniques that they are able to provide high defect tolerance while the amount of area overhead and test/configuration time are kept reasonable.

Keywords

Product Term Molecular Switch Area Overhead Defect Probability Nanoscale Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • M. Tehranipoor
    • R. Rad
      • 1
    1. 1.University of MarylandBaltimore County

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