Built-in Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics
Although complementary metal-oxide semiconductor (CMOS) chips are projected to continue their dominance for another 10—15 years , CMOS technology today faces a number of challenges. Quantum effects will soon make it nearly impossible to further scale devices. Deep sub-micron (DSM) technologies suffer from high leakage, and it is projected that stand-by power and active power for CMOS chips will soon become comparable . Moreover, the high cost associated with chip masks and next-generation fabrication plants poses a formidable economic barrier to commercial nanometer-scale lithography.
KeywordsDefect Density Candidate Block Horizontal Wire Vertical Wire Faulty Block
Unable to display preview. Download preview PDF.
- 1.M. Mishra and S. Goldstein, “Defect Tolerance at the End of the Roadmap,” in Proc. International Test Conference, 2003, pp. 1201-1210.Google Scholar
- 2.E. J. Nowack, “Maintaining the Benefits of CMOS scaling when Scaling Bogs Down,” IBM Journal of Research and Development, no. 2/3, Mar.-May 2002.Google Scholar
- 3.S. C. Goldstein and M. Budiu, “NanoFabrics: Spatial Computing Using Molecular Electronics,” in Proc. International Symposium on Computer Architecture, 2001, pp. 178-189.Google Scholar
- 4.S. C. Goldstein and D. Rosewater, “Digital Logic Using Molecular Electronics,” in Proc. IEEE International Solid State Circuits Conference, vol. 1, 2002, pp. 204-459.Google Scholar
- 5.M. Butts, A. DeHon, and S. C. Goldstein, “Molecular Electronics: Devices, Systems and Tools for Gigagate, Gigabit Chips,” in Proc. International Conference on Computer-Aided Design, 2002, pp. 433-440.Google Scholar
- 8.Nantero Inc., http://www.nantero.com/.
- 9.A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. ComTex Publishing, 1998.Google Scholar
- 10.C. Stroud, S. Konala, P. Chen, and M. Abramovici, “Built-In Self-Test of Logic Blocks in FPGAs (Finally, A Free Lunch: BIST Without Overhead!),” in Proc. IEEE VLSI Test Symposium, 1996, pp. 387-392.Google Scholar
- 11.M. Abramovici, E. Lee, and C. Stroud, “BIST-based Diagnostics for FPGA Logic Blocks,” in Proc. International Test Conference, 1997, pp. 539-547.Google Scholar
- 12.C. Metra, G. Mojoli, S. Pastore, D. Salvi, and G. Sechi, “Novel Technique for Testing FPGAs,” in Proc. Design, Automation and Test in Europe, 1998, pp. 89-94.Google Scholar
- 14.M. B. Tahoori, E. J. McCluskey, M. Renovell, and P. Faure, “A multi- configuration strategy for an application dependent testing of FPGAs,” in Proc. IEEE VLSI Test Symposium, 2004, pp. 154-159.Google Scholar
- 16.W. B. Culbertson, R. Amerson, R. J. Carter, P. Kuekes, and G. Snider, “Defect Tolerance on the Teramac Custom Computer,” in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, 1997, pp. 116-223.Google Scholar
- 18.S. C. Goldstein and D. Rosewater, “What Makes a Good Molecular-Scale Com- puter Device?” School of Computer Science, Carnegie Mellon University, Tech. Rep. CMU-CS-02-181, Sep. 2002.Google Scholar
- 19.J. G. Brown and R. D. S. Blanton, “CAEN-BIST: Testing the NanoFabric,” in Proc. International Test Conference, 2004, pp. 462-471.Google Scholar
- 20.Z. Wang and K. Chakrabarty, “Built-in Self-Test of Molecular Electronics-Based Nanofabrics,” in Proc. European Test Symposium, 2005, pp. 168-173.Google Scholar
- 21.M. Tehranipoor, “Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005, pp. 305-313.Google Scholar
- 22.R. M. Rad and M. Tehranipoor, “SCT: An Approach for Testing and Configuring Nanoscale Devices,” in Proc. IEEE VLSI Test Symposium, 2006 (to appear).Google Scholar
- 25.A. Mabrouk and A. Hubbard, “Design and implementation of an optical test- ing technique for VLSI chips using a potential-sensitive fluorescing dye,” in Proc. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 1997, pp. 568-572.Google Scholar