Designing Nanoscale Logic Circuits Based on Principles of Markov Random Fields

  • K. Nepal
  • R. I. Bahar
  • J. Mundy
  • W. R. Patterson
  • A. Zaslavsky
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

As Si CMOS devices are scaled down into the nanoscale regime, current microarchitecture approaches are reaching their practical limits. Thus far, the semiconductor industry has successfully overcome many hurdles, including the current transition to silicon-on-insulator (SOI) technology [1]. Looking to the future, the next major challenges to Si CMOS include new materials (high-κ and low-κ dielectrics [2]), new device geometries (dual-gate or fin-FET devices [3]), and further downscaling of devices and supply voltages with attendant difficulties in manufacturing, power dissipation, and economics of commodity manufacturing [2]. The longer-term prospects of digital computation then diverge into two interrelated areas. On the system side, there are the computer architecture issues arising from the problem of integrating billions of transistors at the lowest possible supply voltage, with tremendous constraints on total power dissipation and device reliability. On the device integration front, there is hope that hybrid systems will emerge, combining CMOS FETbased digital logic with any number of alternative devices, ranging from analog circuits, to more exotic alternatives (optical sources and detectors, quantum or molecular transistors, carbon nanotube devices, etc.) all on the same chip [4].


Markov Random Field Noise Immunity Soft Error Feedback Path Markov Random 
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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • K. Nepal
    • 1
  • R. I. Bahar
    • 2
  • J. Mundy
    • 2
  • W. R. Patterson
    • 2
  • A. Zaslavsky
    • 2
  1. 1.Department of Electrical EngineeringBucknell UniversityLewisburg
  2. 2.Division of EngineeringBrown UniversityProvidence

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