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Defect-Tolerant Logic with Nanoscale Crossbar Circuits

  • T. Hogg
  • G. Snider
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

Molecular electronics offers the possibility of significantly denser circuits than current lithography-based manufacturing. Achieving this potential requires circuit designs exploiting the capabilities of molecular electronics while compensating for limitations of current fabrication approaches, particularly defects. Creating such circuits in spite of fabrication defects requires economic trade-offs. For instance, accepting lower yields or improving fabrication could reduce defect rates, but increase production cost. Algorithmic configuration strategies for defect-tolerant systems [28], discussed in this chapter, provide higher defect tolerance, but add to manufacturing cost with the additional testing and analysis required. Evaluating this strategy requires determining what defect rates are tolerable at all, i.e., is there some level of defects beyond which constructing circuits is not practical? If we can accommodate defects, how much area overhead is required and how is it affected by choice of circuit geometry? This chapter is an empirical exploration of these questions.

Keywords

Defect Rate Diode Junction Output Wire Input Wire Horizontal Wire 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • T. Hogg
    • 1
  • G. Snider
    • 1
  1. 1.HP LabsPalo Alto

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