Various scenarios for current conduction under breakdown and instability conditions can be realized in the electrostatic discharge (ESD) pulse regime depending on the device design and biasing circuit parameters. Usually, the complexity and nonlinearity of the conductivity modulation processes in the case of ESD events limits the implementation of compact models for direct circuit simulation in ESD pulse conditions. Perhaps for this reason, numerous ESD devices and clamps have been proposed to emphasize a particular feature of the process, device architecture, or specification for the protected pins. Often, these solutions are based on a rather empirical and phenomenological design approach. It is not easy to navigate through numerous publications in the field where devices with the same operation principle have beedn given different names. For example, the same snapback BJT device from bipolar process can be presented in CMOS process under another name-field oxide (FOX) or thick field oxide (TFO) device. At the same time, even in the case of the snapback NPN BJT the device operation can be rather complex due to superposition of the lateral and vertical current conduction.
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© 2008 Springer Science+Business Media, LLC
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(2008). Conductivity Modulation in ESD devices. In: Physical Limitations of Semiconductor Devices. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-74514-5_7
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DOI: https://doi.org/10.1007/978-0-387-74514-5_7
Publisher Name: Springer, Boston, MA
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