Failures of Semiconductor Device
Several typical failure analysis photographs are presented in Fig. 1.1 regarding failed transistor structures. As usual they present somewhat useful information related to the location of the structural damage that identifies the failed devices especially in the case of integrated circuits. Additional information can be derived about the damage location inside the device itself that might reveal or provide an idea regarding some topology defects of the device.
However, perhaps only one of them is directly informative about the physical processes that caused the failure. It is the photo of the GaAs Schottky gate field effect transistor (MESFET) (Fig. 1.1c) that represents a failure due to the tests under electrical load and increased ambient temperature. The formation of emptiness in metallization at the beginning of the source “fingers” and corresponding metal accumulation at the end of the fingers can be observed. The picture is typical of the phenomenon of metal electromigration. In this case it is not essential to be an expert in the field of reliability to diagnose the reason for failure. In most practical cases the final damage quite rarely reveals a direct physical failure mechanism. Often the original cause or complete scenario of failure is hidden by secondary postdamage processes. Thus, it is extremely difficult to restore the failure scenario and particular physical mechanism in order to understand step by step scenario of events resulted to catastrophe. In many cases this problem is excessive even for the experienced researcher. A physical approach to reliability is dictated by a necessity for reliability assessment and maintenance at all stages of the device lifetime cycle. The standard statistical methods are based on confirmation of the required middle time before failure and safe operating area parameters using subsequent statistical processing of the temperature accelerated test and electrical measurement results. Thus, a detailed study of not only direct failure causes, but the dominant physical mechanisms and phenomena that result in particular device failure mode is required during the process, device, and even product development phases.
KeywordsSemiconductor Device Bipolar Transistor Operation Regime Failure Scenario Power Transistor
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