Skip to main content

Interconnection Networks

  • Chapter
  • First Online:
Analysis of Computer and Communication Networks

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 119.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. F. Elguibaly, “Analysis and design of arbitration protocols”, IEEE Transactions on Computers, vol. 38, no. 2, pp. 1168–1175, 1989.

    Google Scholar 

  2. R.J. Simcoe and T.-B. Pei, “Perspectives on ATM switch architecture and the influence of traffic pattern assumptions on switch design”, Computer Communication Review, vol. 25, pp. 93–105, 1995.

    Article  Google Scholar 

  3. N. McKeown, “The iSLIP scheduling algorithm for input-queued switches”, IEEE/ACM Transactions on Networking, vol. 7, pp. 188–201, 1999.

    Article  Google Scholar 

  4. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach, IEEE Computer Society Press, Los Alamito, California, 1997.

    Google Scholar 

  5. J. Walrand, Communication Networks: A First Course, McGraw-Hill, New York, 1998.

    Google Scholar 

  6. M. Swartz, Telecommunication Networks: Protocols, Modeling and Analysis, Addison Wesley, Reading, Massachusetts, 1987.

    Google Scholar 

  7. S.W. Furhmann, “Performance of a packet switch with crossbar architecture”, IEEE Transactions on Communications, vol. 41, pp. 486–491, 1993.

    Article  Google Scholar 

  8. C. Clos, “A study of non-blocking switching networks”, Bell System Technology Journal, vol. 32, pp. 406–424, 1953.

    Google Scholar 

  9. “Performing Internet routing and switching at gigabit speeds”, Cisco 12000 Series GSR Technical Product Description, Cisco Systems, San Jose, California [On line]. Available HTTP: http://www.ieng.com/warp/public/cc/pd/rt/12000/index.shtml

    Google Scholar 

  10. N. McKeown, M. Izzard, A. Mekkittikul, B. Ellersick, and M. Horowitch, “The tiny tera: A small high-bandwidth packet switch core”, IEEE Micro, vol. 17, pp. 26–33, 1997.

    Article  Google Scholar 

  11. C. Partridge, P.P. Carvey, E. Burgess, I. Castineyra, T. Clarke, L. Graham, M. Hathaway, P. Herman, A. King, S. Kohalmi, T. Ma, J. Mcallen, T. Mendez, W.C. Milliken, R. Pettyjohn, J. Rokosz, J. Seeger, M. Sollins, S. Storch, B. Tober, G.D. Troxel, D. Waitzman, and S. Winterble, “A 50 Gb/s IP Router”, IEEE/ACM Transactions on Networking, vol. 6, no. 3, pp. 237–248, 1998.

    Article  Google Scholar 

  12. F. Elguibaly, A. Sabaa and D. Shpak, “A new shift-register based ATM switch”, The First Annual Conference on Emerging Technologies and Applications in Communications (ETACOM), Portland, Oregon, pp. 24–27, May 7–10, 1996.

    Google Scholar 

  13. F. Elguibaly, and S. Agarwal, “Design and performance analysis of shift register-based ATM switch”, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, B.C., pp. 70–73, August 20–22, 1997.

    Google Scholar 

  14. A. Sabaa, F. Elguibaly and D. Shpak, “Design and modeling of a nonblocking input-buffer ATM switch”, Canadian Journal of Electrical and Computer Engineering, vol. 22, no. 3, pp. 87–93, 1997.

    Google Scholar 

  15. V.E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, New York, 1965.

    MATH  Google Scholar 

  16. K. Hwang and F.A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, New York, 1984.

    MATH  Google Scholar 

  17. H.J. Siegel, Interconnection Networks for Large-Scale Parallel Processing: Theory and Case Studies, Lexington Book, Lexington, Massachusetts, 1990.

    Google Scholar 

  18. D. Lawrie, “Access and alignment of data in an array processor”, IEEE Transactions on Computers, vol. C-24, pp. 1145–1155, 1975.

    Article  MathSciNet  Google Scholar 

  19. L.R. Goke and G.J. Lipvski, “Banyan networks for partitioning multiprocessor systems”, First Annual International Symposium on Computer Architecture, pp. 21–28, December 1973.

    Google Scholar 

  20. K. Pibulyarojana, S. Kimura, and Y. Ebihara, “A study on a hybrid dilated banyan network”, IEICE Transaction on Communications, vol. E80 B, pp. 116–126, 1997.

    Google Scholar 

  21. J.H. Patel, “Performance of processor-memory interconnections for multiprocessors”, IEEE Transaction on Computers, vol. C-30, pp. 771–780, 1981.

    Article  Google Scholar 

  22. M. Abd-El-Barr, K. Al-Tawil, and O. Abed, “Fault-tolerant and reliability analysis of multi-stage data manipulator networks”, International Conference on Distributed Computing, pp. 275–280, 1995.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer-Verlag US

About this chapter

Cite this chapter

Gebali, F. (2008). Interconnection Networks. In: Analysis of Computer and Communication Networks. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-74437-7_14

Download citation

  • DOI: https://doi.org/10.1007/978-0-387-74437-7_14

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-74436-0

  • Online ISBN: 978-0-387-74437-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics