The Design of a FPGA-Based Traffic Light Control System: From Theory to Implementation
Most software-defined radio (SDR) prototypes make use of FPGA (Field Programmable Gate Array) devices such as digital filtering that perform operations at high sampling rates. The process from specifications and design to the implementation in FPGA requires the use of a large number of simulation tools. In the first stages of the design, the use of high-level tools such as Matlab, are required to perform intensive simulations. Results will help us to select the best specifications. Once the main design parameters have been established, the overall design is divided into modules following a hierarchical scheme. Each module is defined using a hardware description language (HDL) such as VHDL or Verilog.
In the process of FPGA development, the design is simulated at multiple stages. Initially, each VHDL module is simulated individually by creating test benches to simulate the subsystem and observe the results. After each individual module has been tested, the complete design is integrated and mapped into a netlist which is translated to a gate level description. Once the design is laid out in the FPGA, a simulation stage takes place considering hardware aspects such as propagation delays.
Finally, it is very important to perform cosimulations for the final hardware verification. Cosimulation consists in applying input signals from numerical simulators such as Matlab to hardware components from hardware-based simulators such as ModelSim. Only the inputs and outputs of the hardware component are analyzed to check the performance.
In this paper, we discuss the overall simulation process involved in the implementation of a FPGA-based modem used in a traffic light control system using LEDs (Light Emitting Diodes). The application of LEDs in traffic lights has several advantages with respect to incandescent bulbs in terms of lower power consumption and a number of functions can be implemented: modification of lighting condition depending on climatic conditions, change in the crossing time for pedestrians, failure detection, generation of alarms, etc. In order to implement these applications, the installation of modems in the regulator and traffic lights sites is required.
In our proposal, these modems are implemented in FPGA boards. As an additional innovation, the physical transmission medium is formed by the powerlines connecting the regulator and traffic lights in a star topology. The communication system is based on the EchoNet standard for powerline communication. This specification proposes the use of the CDMA multiple access scheme, which makes the system very robust against impulsive noise interference oftenly found in traffic scenarios.
We have focused on the design flow, making special emphasis on the simulation tools required and the main parameters that must be taken into account to perform an efficient design. In the paper, performance results obtained by simulation and cosimulation will be presented, including parameters of the communication system (BER, frame detection probability) and also result from the hardware simulation tool (power consumption, delays, use of physical resources).
KeywordsTime Slot Field Programmable Gate Array Traffic Light Correlation Peak Impulsive Noise
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