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3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System

  • Chul Kim
  • Alex Rassau
  • Stefan Lachowicz
  • Saeid Nooshabadi
  • Kamran Eshraghian
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

This paper describes the high-level system modeling and functional verification of a novel 3D vertically integrated Adaptive Computing Systemon- Chip (ACSoC), which we term 3D-SoftChip. The 3D-SoftChip comprises two vertically integrated chips (a Configurable Array Processor and an Intelligent Configurable Switch) through an Indium Bump Interconnection Array (IBIA). This paper also describes an advanced HW/SW co-design and verification methodology using SystemC, which has been used to verify the functionality of the system and to allow architectural exploration in the early design stage. An implementation of the MPEG-4 full search block matching motion estimation algorithm has been applied to demonstrate the architectural superiority of the proposed novel 3D-ACSoC.

Keywords

Processing Element Candidate Block Processing Element Array Search Position Adaptive Computing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

7 References

  1. 1.
    Chul Kim et al, 3D-SoftChip: A Novel Architecture for Next Generation Adaptive Computing systems, EURASIP Journal on Applied Signal Processing, Volume 2006, Article ID 75032, (Feb. 2006), pp.1-13Google Scholar
  2. 2.
    S. Eshraghian, S. Lachowicx, K. Eshraghian, 3D-Vertically Integrated Configurable Soft-Chip with Terabit Computational Bandwidth for Image and Data Processing, Proc. MIXDES’2003, (June 2003), pp.26-28Google Scholar
  3. 3.
    J.W. Joyner, et al, Impact of three-dimensional architectures on interconnects in gigascale integration, IEEE Trans. VLSI Syst. Vol9, (Dec. 2001), pp.922-928CrossRefGoogle Scholar
  4. 4.
    Joyner J.W, Zarkesh-Ha P.J, Meindl J.D, Global Interconnect Design in a ThreeDimensional System-on-a-Chip, IEEE Trans. on VLSI Systems, Vol. 12, Issue 4, (April 2004), pp.367-372CrossRefGoogle Scholar
  5. 5.
  6. 6.
    Kaustv Banerjee, et al, 3-D ICs: A Novel Chip Design for Improving DeepSubmicrometer Interconnection, Proceedings IEEE Special Issues on Interconnections, Vol. 89, No 5, (May 2001), pp.602-633Google Scholar
  7. 7.
    C. Ebeling et al, Architecture design of reconfigurable pipelined datapaths, Advanced Research I VLSI, Proceeding 20th Anniversary Conference on (March 1999), pp.23-40, 21-40Google Scholar
  8. 8.
    E. Waingold et al, Bring it all to software: RAW Machines, Computer, Vol.30, Issue9 (Sept. 1997) pp.86-93Google Scholar
  9. 9.
    S. Hartej, L. Ming-hua, L. Guangming, J.K. Fadi, B. Nadar, M.C.F Eliseu, MorphoSys: An Integrated reconfigurable system for data-parallel and computation-intensive applications, IEEE Trans. on Computers, (May 2000), pp.456-481Google Scholar
  10. 10.
    QuickSilver Technology Inc., Adapt2400 ACM Architecture Overview; http://www.quicksilvertech.com/pdfs/Adapt2400_Whitepaper_0404.pdf
  11. 11.
    Elixent Ltd, The Reconfigurable Algorithm Processor; http://www.elixent.com/products/white_papers.htm
  12. 12.
    picoChip Design Limited, PC102 Product Brief; http://www.picochip.com
  13. 13.
    S. Eshraghian, Implementation of Arithmetic Primitives using Truly Deep Submicro Technology (TDST), Ms. Thesis, Edith Cowan University, (2004)Google Scholar
  14. 14.
    L. Guangming, Modeling, Implementation and Scalability of the MorphoSys Dynamically Reconfigurable Computing Architecture, PhD Thesis, University of California, Irvine, (2000)Google Scholar
  15. 15.
    Open SystemC Initiative, SystemC 2.0.1 Language Reference Manual Rev. 1.0; http://www.systemc.org
  16. 16.
    Hartej Singh, Reconfigurable Architectures for Multimedia and Data-Parallel Application Domains, PhD Thesis, University of California, Irvine, (2000)Google Scholar
  17. 17.
    Texas Instruments, TMS320C6000 Assembly Benchmarks; http://www.ti.com/sc/docs/products/dsp/c6000/benchmarks/67x.htm
  18. 18.
    K.M. Yang, M-T. Sun and L.Wu, A Family of VLSI Design of Motion Compensation Block Matching Algorithm, IEEE Trans. on Circuits and Systems, Vol 36, No.10, (October 1999), pp.1317-25Google Scholar
  19. 19.
    C. Hsieh and T. Lin, VLSI Architecture for Block Matching Motion Estimation Algorithm, IEEE Trans. on Circuits and Systems for Video Technology, Vol2, (June 1992), pp.167-175Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Chul Kim
    • 1
  • Alex Rassau
    • 1
  • Stefan Lachowicz
    • 1
  • Saeid Nooshabadi
    • 2
  • Kamran Eshraghian
    • 3
  1. 1.Centre for Very High Speed Microelectronic Systems, School of Engineering and MathematicsEdith Cowan UniversityPerthAustralia
  2. 2.School of Electrical Engineering and TelecommunicationsThe University of New South WalesSydneyAustralia
  3. 3.Technology ParkEshraghian Laboratories Pty Ltd.BentleyAustralia

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