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Defragmentation Algorithms for Partially Reconfigurable Hardware

  • Markus Koester
  • Heiko Kalte
  • Mario Porrmann
  • Ulrich Rückert
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. Standard platforms for partial dynamic reconfiguration are field-programmable gate arrays (FPGAs). Multiple hardware tasks can share the same FPGA resources over time, which increases the device utilization in comparison to non-reconfigurable systems. Although, similar resource management is already known in the area of operating systems, there is a requirement to adapt these concepts to the special needs of dynamically reconfigurable systems. Additionally, there is a lack of underlying mechanisms, e.g., to suspend hardware tasks and restart them at a different position within the FPGA. In this article we introduce a mechanism for task relocation that includes saving and restoring of state information of the task. Based on this approach we address the problem of defragmentation. We present defragmentation algorithms that minimize different types of costs. With the help of a detailed simulation model and a benchmark, we finally provide realistic simulation results and compare the different algorithms.

Keywords

Cell Column Relocation Process FPGA Resource Device Utilization Virtex FPGAs 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Markus Koester
    • 1
  • Heiko Kalte
    • 2
  • Mario Porrmann
    • 1
  • Ulrich Rückert
    • 1
  1. 1.Heinz Nixdorf Institute, System and Circuit TechnologyUniversity of PaderbornGermany
  2. 2.School of Computer Science and Software EngineeringUniversity of Western AustraliaAustralia

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