A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

  • Leonardo L. de Oliveira
  • Cristiano Santos
  • Daniel Ferrão
  • Eduardo Costa
  • José Monteiro
  • João Baptista Martins
  • Sergio Bampi
  • Ricardo Reis
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

This paper presents performance comparisons between two multipliers architectures. The first architecture consists of a pure array multiplier that was modified to handle the sign bits in 2’s complement and uses a radix-4 encoding to reduce the partial product lines. The second architecture implemented was the widely used Modified Booth multiplier. We describe a design methodology to physically implement these architectures in a pipelined and non-pipelined form, obtaining area, power consumption and delay results. Up to now only results at the logic level were presented in previous work. The performance of pipelined array architecture is compared with the pipelined Modified Booth. We compare the physical implementations in terms of area, power and delay. The results show that the new pipelined array multiplier can be significantly more efficient, with close to 16% power savings and 55% power savings when considering non-pipelined architectures.


Power Saving Partial Product Logic Level Full Adder Array Architecture 
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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Leonardo L. de Oliveira
    • 1
  • Cristiano Santos
    • 2
  • Daniel Ferrão
    • 2
  • Eduardo Costa
    • 3
  • José Monteiro
    • 4
  • João Baptista Martins
    • 1
  • Sergio Bampi
    • 2
  • Ricardo Reis
    • 2
  1. 1.Federal University of Santa Maria, PPGEE – GMICROCamobiBrazil
  2. 2.Federal University of Rio Grande do Sul, PPGC – GMEAgronomiaBrazil
  3. 3.Catolic University of PelotasBrazil
  4. 4.INESC-ID/ISTPortugal

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