Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals

  • Fraidy Bouesse
  • Marc Renaudin
  • Gilles Sicard
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data processing times. The efficiency of the countermeasure, in terms of DPA resistance, is formally presented and analyzed. Electrical simulations performed on a DES crypto-processor confirm the relevancy of the approach, showing a drastic reduction of the DPA peaks, thus increasing the complexity of a DPA attack on QDI asynchronous circuits.


Random Number Generator Acknowledgment Signal Data Encryption Standard Asynchronous Module Differential Power Analysis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Fraidy Bouesse
    • 1
  • Marc Renaudin
    • 2
  • Gilles Sicard
    • 1
  1. 1.Concurent Integrated Systems GroupTIMA LaboratoryFrance
  2. 2.Concurent Integrated Systems GroupTechniques of Informatics and Microelectronics for Computer Architecture Laboratory (TIMA)France

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