The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data processing times. The efficiency of the countermeasure, in terms of DPA resistance, is formally presented and analyzed. Electrical simulations performed on a DES crypto-processor confirm the relevancy of the approach, showing a drastic reduction of the DPA peaks, thus increasing the complexity of a DPA attack on QDI asynchronous circuits.
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7 References
P. Kocher, J. Jaffe, B. Jun, “Differential Power Analysis,” Advances in Cryptology -Crypto 99 Proceedings, Lecture Notes In Computer Science Vol. 1666, M. Wiener ed., Springer-Verlag, 1999.
Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, George Taylor, “Improving Smart Card Security using Self-timed Circuits”, Eighth International Symposium on Asynchronous Circuits and systems (ASYNC2002). 8-11 April 2002. Manchester, U.K.
L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside and S. Temple, “SPA -A Synthesisable Amulet Core for Smartcard Applications”, Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). Pages 201-210. Manchester, 8-11/04/2002. Published by the IEEE Computer Society.
Jacques J. A Fournier, Simon Moore, Huiyun Li, Robert Mullins, and Gerorge Taylor,“Security Evalution of Asunchronous Circuits”, CHES 2003, LNCS 2779, pp 137-151, 2003.
F. Bouesse, M. Renaudin, B. Robisson, E Beigne, P.Y. Liardet, S. Prevosto, J. Sonzogni, “DPA on Quasi Delay Insensitive Asynchronous circuits: Concrete Results”, To be published in XIX Conference on Design of Circuits and Integrated Systems Bordeaux, France, November 24-26, 2004.
G.F. Bouesse, M. Renaudin, S. Dumont, F. Germain, « DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement », DATE 2005. p. 424
T. S. Messerges and E. A. Dabbish, R. H. Sloan, “Investigations of Power Analysis Attacks on Smartcards”, USENIX Workshop on Smartcard Technology, Chicago, Illinois, USE, May 10-11, 1999.
Marc Renaudin, “Asynchronous circuits and systems: a promising designalternative”, Microelectronic for Telecommunications : managing high complexity and mobility” (MIGAS 2000), special issue of the Microelectronics-Engineering Journal, Elsevier Science, GUEST Editors : P; Senn, M. Renaudin, J, Boussey, Vol. 54, N° 1-2, December 2000, pp. 133-149.
Viktor Fischer, M. Drutarovský, True Random Number Generator Embedded in Reconfigurable Hardware, In C. K. Koç, and C. Paar, (Eds.): Cryptographic Hardware and Embedded Systems (CHES 2002), Redwood Shore, USA, LNCS No. 2523, Springer, Berlin, Germany, ISBN 3-540-00409-2, pp. 415-430.
V. Fischer, M. Drutarovský, M. Šimka, N. Bochard, High Performance True Random Number Generator in Altera Stratix FPLDs, in J. Becker, M. Platzner, S. Vernalde (Eds.): “Field-Programmable Logic and Applications,” 14th International Conference, FPL 2004, Antwerp, Belgium, August 30-September 1, 2004, LNCS 3203, Springer, Berlin, Germany, pp. 555-564.
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Bouesse, F., Renaudin, M., Sicard, G. (2007). Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. In: Reis, R., Osseiran, A., Pfleiderer, HJ. (eds) Vlsi-Soc: From Systems To Silicon. IFIP International Federation for Information Proc, vol 240. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73661-7_2
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