On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction

  • Thilo Pionteck
  • Thomas Stiefmeier
  • Thorsten Staake
  • Manfred Glesner
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed- Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.


Clock Cycle Error Detection Advance Encryption Standard Cyclic Redundancy Check RISC Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Thilo Pionteck
    • 1
  • Thomas Stiefmeier
    • 2
  • Thorsten Staake
    • 3
  • Manfred Glesner
    • 4
  1. 1.Institute of Computer EngineeringUniversity of LübeckGermany
  2. 2.Wearable Computing LabETH ZürichSwitzerland
  3. 3.Institute of Technology ManagementUniversity of St.GallenSwitzerland
  4. 4.Institute of Microelectronic SystemsDarmstadt University of TechnologyGermany

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