Scan technology increases the switching activity well beyond that of the functional operation of an IC. In this paper, we first discuss the issues of excessive peak power during scan testing and highlight the importance of reducing peak power particularly during the test cycle (i.e. between launch and capture) so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we propose a scan cell reordering solution to minimize peak power during all test cycles of a scan testing process. The problem of scan cell reordering is formulated as a constrained global optimization problem and is solved by using a simulated annealing algorithm. Experimental evidence and practical implications of the proposed solution are given at the end of the paper. For ISCAS’89 and ITC’99 benchmark circuits, this approach reduces peak power during TC up to 51% compared to an ordering provided by an industrial synthesis tool. Fault coverage and test time are left unchanged by the proposed solution.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Semiconductor Industry Association (SIA), “International Technology Roadmap for Semiconductors (ITRS)”, 2005 Edition.
M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing”, Kluwer Academic Publishers, 2000.
C. Shi and R. Kapur, “How Power Aware Test Improves Reliability and Yield”, IEEDesign.com, September 15, 2004.
J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash and M. Hachinger, “A Case Study of IR-Drop in Structured At-Speed Testing”, IEEE International Test Conference, pp. 1098-1104, 2003.
V. Dabholkar, S. Chakravarty, I. Pomeranz and S.M. Reddy, “Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuits”, IEEE Transactions on CAD, Vol. 17, N° 12, pp. 1325-1333, December 1998.
Y. Bonhomme, P. Girard, C. Landrault and S. Pravossoudovitch, “Power Driven Chaining of Flip-flops in Scan Architectures”, IEEE Int'l Test Conf., pp. 796-803, 2002.
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault and S. Pravossoudovitch, “Efficien t Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint”, IEEE Int'l Test Conf., pp. 488-493, 2003.
P. Girard, “Survey of Low-Power Testing of VLSI Circuits”, IEEE Design & Test of Computers, Vol. 19, N° 3, pp. 82-92, May-June 2002.
N. Nicolici and B. Al-Hashimi, “Power-Constrained Testing of VLSI Circuits”, Springer Publishers, 2003.
K.M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques”, IEEE Int'l Test Conf., pp. 355-364, 2004.
TetraMAX™, Version 2001.08, Synopsys Inc., 2001.
PowerMill®, Version 5.4, Synopsys Inc., 2000.
R. Sankaralingam, R. Oruganti and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation”, IEEE VLSI Test Symp., pp. 35-42 , 2000.
“Modern Heuristic Techniques for Combinatorial Problems”, Edited by C.R. Reeves, Backwell Scientific Publications, 1993.
S. Kirkpatrick, C. D. Gelatt Jr., M. P. Vecchi, “Optimization by Simulated Annealing”, Science, 220, 4598, 671-680, 1983.
M. Hirech, J. Beausang and X. Gu, “A New Approach to Scan Chain Reordering Using Physical Design Information”, IEEE Int'l Test Conf., pp. 348-355, 1998.
D. Berthelot, S. Chaudhuri and H. Savoj, “An Efficient Linear-Time Algorithm for Scan Chain Optimization and Repartitioning”, IEEE Int'l Test Conf., pp. 781-787, 2002.
“Silicon Ensemble®”, Cadence Design System, 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer Science+Business Media, LLC
About this paper
Cite this paper
Badereddine, N., Girard, P., Pravossoudovitch, S., Virazel, A., Landrault, C. (2007). Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. In: Reis, R., Osseiran, A., Pfleiderer, HJ. (eds) Vlsi-Soc: From Systems To Silicon. IFIP International Federation for Information Proc, vol 240. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73661-7_17
Download citation
DOI: https://doi.org/10.1007/978-0-387-73661-7_17
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-73660-0
Online ISBN: 978-0-387-73661-7
eBook Packages: Computer ScienceComputer Science (R0)