A Traffic Injection Methodology with Support for System-Level Synchronization

  • Shankar Mahadevan
  • Federico Angiolini
  • Jens Sparsø
  • Luca Benini
  • Jan Madsen
Conference paper
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

In highly parallel Multi-Processor System-on-Chip (MPSoC) design stages, interconnect performance is a key optimization target. To effectively achieve this objective, true-to-life IP core traffic must be injected and analyzed. However, the parallel development of MPSoC components may cause IP core models to be still unavailable when tuning communication performance. Traditionally, synthetic traffic generators have been used to overcome such an issue. However, target applications increasingly present non-trivial execution flows and synchronization patterns, especially in presence of underlying operating systems and when exploiting interrupt facilities. This property makes it very difficult to generate realistic test traffic. This paper presents a selection of application flows, representative of a wide class of applications with complex interruptbased synchronization; a reference methodology to split such applications in execution subflows and to adjust the overall execution stream based upon hardware events; a reactive simulation device capable of correctly replicating such software behaviours in the MPSoC design phase. Additionally, we validate the proposed concept by showing cycle-accurate reproduction of a previously traced application flow.


Execution Trace Program Counter Design Automation Conference Interrupt Handling 38th Design Automation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Shankar Mahadevan
    • 1
  • Federico Angiolini
    • 2
  • Jens Sparsø
    • 1
  • Luca Benini
    • 2
  • Jan Madsen
    • 1
  1. 1.Informatics and Mathematical ModellingTechnical University of DenmarkDenmark
  2. 2.Dipartimento di Eletronica, Informatica e Sistemisticand MathematicsUniversity of BolognaItaly

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