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Circuit Verification

  • Wolfgang Rülling
Chapter

Abstract

There are several concepts of how to verify the correctness of a circuit. Since designing and manufacturing integrated circuits are very time-consuming and expensive tasks it is necessary to detect errors as soon as possible in order to avoid additional costs (e.g., see [9.2]).

Keywords

Critical Path Design Error Clock Rate Logic Block Programmable Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [9.1]
    Eveking, E.; Hinrichsen, H.; Ritter, G.: ‘Automatic Verification of Scheduling Results in High-Level Synthesis.’ DATE’99, 1999Google Scholar
  2. [9.2]
    Fournier, L.; Arbetman, Y.; Levinger, M.: ‘Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator.’ DATE’99, 1999Google Scholar
  3. [9.3]
    Hendricx, S.; Claesen, L.: ‘Formally Verified Redundancy Removal.’ DATE’99, 1999Google Scholar
  4. [9.4]
    Lipsett, R.; Schaefer, C.; Ussery, C.: ‘VHDL: Hardware Description and Design.’ Kluwer Academic Publishers, 1989Google Scholar
  5. [9.5]
    Ten Hagen, K.: ‘Abstrakte Modellierung digitaler Schaltungen.’ Berlin: Springer Verlag, 1995Google Scholar

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Wolfgang Rülling

There are no affiliations available

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