Tabular Design Formats

  • Gert Voland


Netlists describe circuits in a textual list format. They are normally of structural type and have two main targets:
  • Enumeration of all devices (or parts) including the input and output pins;

  • Enumeration of all connections between the device pins.


Head Section Delay Data Mentor Graphic Version EDIF Schematic Editor 


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  1. [8.1]
    Tuinenga, P. W.: ‘SPICE, A Guide to Circuit Simulation & Analysis Using PSPICE’.–Englewood Cliffs, NJ: Prentice Hall, 1992Google Scholar
  2. [8.2]
    EDIF, Electronic Design Interchange Format, Version 2 0 0’. EIA EDIF Steering Committee, 1989Google Scholar
  3. [8.3]
    EDIF Technical Centre:
  4. [8.4]
    Accellera Interest Group:
  5. [8.5]
    Standard Delay Format Specification, Version 2.1. Open Verilog International:

Copyright information

© Springer Science+Business Media New York 2003

Authors and Affiliations

  • Gert Voland

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