Netlists describe circuits in a textual list format. They are normally of structural type and have two main targets:
Enumeration of all devices (or parts) including the input and output pins;
Enumeration of all connections between the device pins.
KeywordsHead Section Delay Data Mentor Graphic Version EDIF Schematic Editor
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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- [8.1]Tuinenga, P. W.: ‘SPICE, A Guide to Circuit Simulation & Analysis Using PSPICE’.–Englewood Cliffs, NJ: Prentice Hall, 1992Google Scholar
- [8.2]EDIF, Electronic Design Interchange Format, Version 2 0 0’. EIA EDIF Steering Committee, 1989Google Scholar
- [8.3]EDIF Technical Centre: http://www.edif.org
- [8.4]Accellera Interest Group: http://www.ovi.org
- [8.5]Standard Delay Format Specification, Version 2.1. Open Verilog International: http://www.eda.org
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