Geometric Verification

  • Harald Toepfer


The term Geometric Verification subsumes different checks executing at the finished layout or during the design of the layout. Most important is the DesignRuleCheck. It verifies the minimum spaces and widths in the layout prescribed by the manufacturer.


Parasitic Capacity Logic Combination Electrical Rule Recognition Layer Fringe Capacity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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    Baker, R. J.; Li, H. W.; Boyse, D. E.: ‘CMOS Circuit Design, Layout and Simulation’. IEEE-Press, 1998Google Scholar
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    Smith, M. J. S.: ‘Application-Specific Integrated Circuits’.–Addison-Wesley, 1997Google Scholar

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© Springer Science+Business Media New York 2003

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  • Harald Toepfer

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