The Concept of Electronic Design Automation

  • Alfred Schütz


The design of an integrated circuit (IC, chip) can be an extremely complicated task and requires a structured approach. In short, this endeavor is nothing else than the transformation of a mixed electric/logic specification into geometrical patterns suited for mass production. Today such patterns are usually printed onto a set of masks (also called reticles) shaping an image which will be optically projected onto a photographic film layer deposited at the surface of the chip. For a typical CMOS technology the number of masks may range from 12 up to 30 (the main reason for more mask layers required being the number of wiring layers). The geometrical patterns on those masks are represented by a large number of polygons each characterized by its corner points. With the broad scope of ASICs today, the total number of the points can vary widely. For instance, an ASIC with 1,000,000 gates (which can be considered a commodity in these days rather than advanced) comprises some 200 million points. Needless to say, the coordinates of each point are meaningful, the proper function of the chip is in question if a particular point is offset.


Clock Cycle Register Transfer Level Gate Level Automatic Test Pattern Generation Static Timing Analysis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media New York 2003

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  • Alfred Schütz

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