Design for Testability

  • Wolfgang Rülling


This section gives an overview of various aspects of testing chips. It considers the modeling of errors, automatic test pattern generation, and how to design circuits that can easily been tested. Usually in ASIC design systems there are special tools for supporting the testing of chips. Examples are the programs Quick-Fault and Fast-Scan from Mentor Graphics, Verifault from Cadence and TestCompiler from Synopsys. Additionally, synthesis tools typically support Scan Path and Boundary Scan techniques (sections 15.5 and 15.7). Section 15.6 gives some more specialized test structures which may be implemented by the chip designer, or are already part of parameterized cell generators.


Fault Model Test Pattern Primary Input Fault Coverage Linear Feedback Shift Register 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media New York 2003

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  • Wolfgang Rülling

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