Tutorial II: Sequential Design and Hierarchy

Chapter 4 is a short CAD tool tutorial that serves as both a hierarchical and sequential design example. A counter is clocked by a pushbutton and the output is displayed in the seven-segment LEDs. The design is downloaded to the FPGA board and some real world timing issues arising from switch contact bounce are resolved. It uses several functions from the FPGAcore library which greatly simplify use of the FPGA’s input and output capabilities.

The second tutorial contains a more complex design containing sequential logic and hierarchy with a counter and a Hex display. To save time, much of the design has already been entered. The existing design will require some modifications. Once again, any of the Altera educational FPGA boards can be used.


Sequential Design Logic Circuit Clock Input Board Type FPGA Board 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer Science+Business Media, LLC 2008

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