Tutorial IV: Nios II Processor Hardware Design
Chapter 17 contains a tutorial on the processor core hardware configuration tool, SOPC builder. A DE2, DE1, or FPGA board is required for this new material since it is not supported on the UP2 or UP1’s smaller FPGA.
Designing systems with embeddeded processors requires both hardware and software design elements. A collection of CAD tools developed by Altera enable you to design both the hardware and software for a fully functional, customizable, soft-core processor called Nios II. This tutorial steps you through the hardware implementation of a Nios II processor for the DE1 and DE2 boards, and Tutorial III (in the preceding chapter) introduces the software design tools for the Nios II processor.
KeywordsRapid Prototype Flash Memory Hardware Design Memory Controller FPGA Board
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