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Introducing System-on-a-Programmable-Chip

A new technology has emerged that enables designers to utilize a large FPGA that contains both memory and logic elements along with an intellectual property (IP) processor core to implement a computer and custom hardware for system-on-a-chip (SOC) applications. This new approach has been termed system-on-a-programmable-chip (SOPC).

Keywords

Processor Core External Memory Hardware Description Language Autopilot System Soft Processor Core 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. Portions reprinted, with permission, from T. S. Hall and J. O. Hamblen, “System-on-a-Programmable-Chip Development Platforms in the Classroom,” IEEE Transactions on Education, vol. 47, no. 4, pp. 502-507, Nov. 2004. © 2004 IEEE.Google Scholar
  2. D. Seguine, “Just add sensor - integrating analog and digital signal conditioning in a programmable system on chip,” Proceedings of IEEE Sensors, vol. 1, pp. 665–668, 2002. M. Mar, B. Sullam, and E. Blom, “An architecture for a configurable mixed-signal device,” IEEE J. Solid-State Circuits, vol. 38, pp. 565–568, Mar. 2003.Google Scholar
  3. H. Chang et al., Surviving the SOC Revolution a Guide to Platform-Based Design. Norwell, MA: Kluwer, 1999.Google Scholar
  4. This speed is not achievable on all devices for either processor core. Some FPGAs may limit the maximum frequency to as low as 50 MHz.Google Scholar
  5. In very large quantities.Google Scholar
  6. Henrik B. Christophersen; R. W. Pickell; James C. Neidhoefer; Adrian A. Koller; Suresh K. Kannan; Eric N. Johnson, “A Compact Guidance, Navigation, and Control System for Unmanned Aerial Vehicles”, Journal of Aerospace Computing, Information, and Communication, pp.,1542-9423, vol.3 no.5.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

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