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A RISC Design: Synthesis of the MIPS Processor Core

Chapter 14 describes a single clock cycle model of the MIPS RISC processor based on the hardware implementation presented in the widely used Patterson and Hennessy textbook, Computer Organization and Design the Hardware/Software Interface. Laboratory exercises that add new instructions, features, and pipelining are included at the end of the chapter.

The MIPS is an example of a modern reduced instruction set computer (RISC) developed in the 1980s. The MIPS instruction set is used by NEC, Nintendo, Motorola, Sony, and licensed for use by numerous other semiconductor manufacturers. It has fixed-length 32-bit instructions and thirty-two 32-bit general-purpose registers. Register 0 always contains the value 0. A memory word is 32 bits wide.

Keywords

Rapid Prototype Clock Cycle Register File Data Memory Program Counter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer Science+Business Media, LLC 2008

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