Tutorial I: The 15 Minute Design

Chapter 1 is a short CAD tool tutorial that covers design entry, simulation, and hardware implementation using an FPGA. The majority of students can enter the design, simulate, and have the design successfully running on the FPGA board in less than thirty minutes. After working through the tutorial and becoming familiar with the process, similar designs can be accomplished in less than 10 minutes.

The purpose of this tutorial is to introduce the user to the Altera CAD tools and the University Program (DE1, DE2, UP3, UP2, or UP1) FPGA Development Boards in the shortest possible time. The format is an aggressive introduction to schematic, VHDL, and Verilog entry for those who want to get started quickly. The approach is tutorial and utilizes a path that is similar to most digital design processes.