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Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes

  • Dominik Murr
  • Felix Mühlbauer
  • Falko Dressler
  • Christophe Bobda
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)

Keywords

Sensor Network Sensor Node Network Node Hardware Accelerator Hardware Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
    Linux on ppc. http://penguinppc.org/.
  2. [2]
  3. [3]
    Digilent Inc. The vdec1 video decoder board.Google Scholar
  4. [4]
    Brian P. Gerkey and Maja J Matarić. Sold!: Auction methods for multi-robot coordination. IEEE Transactions on Robotics and Automation, 18(5):758-768, October 2002.CrossRefGoogle Scholar
  5. [5]
    Intel. imote isn100-ba data sheet.Google Scholar
  6. [6]
    D. Martin, A. Cheyer, and D. Moran. The Open Agent Architecture: a framework for building distributed software systems. Applied Artificial Intelligence, 13(1/2):91-128, 1999.Google Scholar
  7. [7]
    moteiv. Tmote sky homepage.Google Scholar
  8. [8]
    Jingzhao Ou and Viktor K. Prasanna. Rapid energy estimation of computations on fpga based soft processors. In IEEE International SoC Conference (SOCC), 2004.Google Scholar
  9. [9]
    R. Shah and J. Rabaey. Energy aware routing for low energy ad hoc sensor networks, 2002.Google Scholar
  10. [10]
    Suresh Singh, Mike Woo, and C. S. Raghavendra. Power-aware routing in mobile ad hoc networks. In Mobile Computing and Networking, pages 181-190, 1998.Google Scholar
  11. [11]
    MontaVista Software. Montavista linux professional 3.1. http://www.mvista.com/.
  12. [12]
    John W. Williams and Neil Bergmann. Embedded linux as a platform for dynamically self-reconfiguring systems-on-chip. In Toomas P. Plaks, editor, ERSA04: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, pages 163-169, Las Vegas, Nevada, USA, June 2004. CSREA Press.Google Scholar
  13. [13]
  14. [14]
    Xilinx Inc. Early access partial reconfiguration user guide. Xilinx User Guide UG208, Version 1.1, March 6, 2006.Google Scholar
  15. [15]
    Xilinx Inc. Homepage. http://www.xilinx.com/.
  16. [16]
    Xilinx Inc. Ml403 evaluation platform. http://www.xilinx.com/products/boards/ml403/docs.htm.
  17. [17]
    Xilinx Inc. Two flows for partial reconfiguration: Module based or difference based. Xilinx Application Note XAPP290, Version 1.1, 2003.Google Scholar
  18. [18]
    Xilinx Inc. Virtex-ii pro xup development board. http://www.xilinx.com/univ/xupv2p.html.

Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  • Dominik Murr
    • 1
  • Felix Mühlbauer
    • 2
  • Falko Dressler
    • 3
  • Christophe Bobda
    • 4
  1. 1.Self-Organizing Embedded Systems Group Department of Computer ScienceKaiserslautern University of TechnologyGermany
  2. 2.Self-Organizing Embedded Systems Group Department of Computer ScienceKaiserslautern University of TechnologyGermany
  3. 3.Computer Networks and Communication Systems Department of Computer ScienceFriedrich-Alexander UniversityGermany
  4. 4.Self-Organizing Embedded Systems Group Department of Computer ScienceKaiserslautern University of TechnologyGermany

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