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Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs

  • Fabrizio Ferrandi
  • Luca Fossati
  • Marco Lattuada
  • Gianluca Palermo
  • Donatella Sciuto
  • Antonino Tumeo
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)

Keywords

Field Programmable Gate Array Task Graph Intermediate Representation Target Architecture Preceding Task 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  • Fabrizio Ferrandi
    • 1
  • Luca Fossati
    • 2
  • Marco Lattuada
    • 3
  • Gianluca Palermo
    • 4
  • Donatella Sciuto
    • 5
  • Antonino Tumeo
    • 6
  1. 1.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly
  2. 2.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly
  3. 3.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly
  4. 4.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly
  5. 5.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly
  6. 6.Dipartimento di Elettronica e InformazionePolitecnico di MilanoItaly

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