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An Interactive Design Environment for C-based High-Level Synthesis

  • Dongwan Shin
  • Andreas Gerstlauer
  • Rainer Dömer
  • Daniel D. Gajski
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)

Keywords

Clock Period Register Transfer Level Synthesis Tool Read Port Embed Computer System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  • Dongwan Shin
    • 1
  • Andreas Gerstlauer
    • 2
  • Rainer Dömer
    • 3
  • Daniel D. Gajski
    • 4
  1. 1.Center for Embedded Computer SystemsUniversity of CaliforniaIrvineUSA
  2. 2.Center for Embedded Computer SystemsUniversity of CaliforniaIrvineUSA
  3. 3.Center for Embedded Computer SystemsUniversity of CaliforniaIrvineUSA
  4. 4.Center for Embedded Computer SystemsUniversity of CaliforniaIrvineUSA

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