Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures

  • Shanghua Gao
  • Kenshu Seto
  • Satoshi Komatsu
  • Masahiro Fujita
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)


Integer Linear Programming Clock Cycle Finite State Machine Data Path Clock Period 
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Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  • Shanghua Gao
  • Kenshu Seto
  • Satoshi Komatsu
  • Masahiro Fujita

There are no affiliations available

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