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Requirements and Concepts for Transaction Level Assertion Refinement

  • Wolfgang Ecker
  • Volkan Esen
  • Thomas Steininger
  • Michael Velten
Part of the IFIP – The International Federation for Information Processing book series (IFIPAICT, volume 231)

Keywords

Abstraction Level Delay Operator Transaction Level Mixed Level Transaction Level Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [1]
  2. [2]
    N. Bombieri, A. Fedeli, and F. Fummi. On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. In 6th International Workshop on Microprocessor Test and Verification (MTV), November 2005.Google Scholar
  3. [3]
    N. Bombieri, F. Fummi, and G. Pravadelli. On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL. In 9th International Conference on Design, Automation and Test in Europe (DATE), March 2006.Google Scholar
  4. [4]
    L. Cai and D. Gajski. Transaction Level Modeling: An Overview. In 1st International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), October 2003.Google Scholar
  5. [5]
    X. Chen, Y. Luo, H. Hsieh, L. Bhuyan, and F. Balarin. Assertion Based Verification and Analysis of Network Processor Architectures. Design Automation for Embedded Systems, 2004.Google Scholar
  6. [6]
    Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, and Michael Velten. Requirements and Concepts for Transaction Level Assertions. In 24th International Conference on Computer Design (ICCD), California, USA, October 2006.Google Scholar
  7. [7]
    Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, and Michael Velten. Specification Language for Transaction Level Assertions. In 11th IEEE International High Level Design Validation and Test Workshop (HLDVT), Monterey, California, Nov. 2006.Google Scholar
  8. [8]
    H. Foster, E. Marschner, and Y. Wolfsthal. IEEE 1850 PSL: The Next Generation. http://www.pslsugar.org/papers/ieee1850psl-thenext generation.pdf.
  9. [9]
    A. Habibi and S. Tahar. On the extension of SystemC by SystemVerilog Assertions. In Canadian Conference on Electrical & Computer Engineering, volume 4, pages 1869-1872, Niagara Falls, Ontario, Canada, May 2004.Google Scholar
  10. [10]
    A. Habibi and S. Tahar. Towards an Efficient Assertion Based Verification of SystemC Designs. In In Proc. of the High Level Design Validation and Test Workshop, pages 19-22, Sonoma Valley, California, USA, November 2004.Google Scholar
  11. [11]
    IEEE Computer Society. SystemVerilog LRM P1800. http://www.ieee.org.
  12. [12]
    Andrew Ireland. Towards Automatic Assertion Refinement for Separation Logic. In 21 st International Conference on Automated Software Engineering (ASE), September 2006.Google Scholar
  13. [13]
    B. Niemann and C. Haubelt. Assertion Based Verification of Transaction Level Models. In ITG/GI/GMM Workshop, volume 9, pages 232-236, Dresden, Germany, February 2006.Google Scholar
  14. [14]
    T. Peng and B. Baruah. Using Assertion-based Verification Classes with SystemC Verification Library. Synopsys Users Group, Boston, 2003.Google Scholar

Copyright information

© International Federation for Information Processin 2007

Authors and Affiliations

  • Wolfgang Ecker
    • 1
  • Volkan Esen
  • Thomas Steininger
  • Michael Velten
  1. 1.IFAG COM BTS MT SDInfineon Technologies AGGermany

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