Advertisement

Side-Channel Resistant Circuit Styles and Associated IC Design Flow

  • Kris Tiri
Chapter
Part of the Integrated Circuits and Systems book series (ICIR)

Abstract

The supply current variations, which are being analyzed to find the secret information, are the aggregated effect of the supply current variations of the individual switching logic gates that make up the microcontroller- or ASIC-based encryption system under attack. The fundamental reason that the information is leaked through the power supply is that the logic gates have an asymmetric power consumption. Indeed, as discussed in Section 2.1, only when the output of the logic gate makes a 0–1 transition, a current comes from the power supply and charges the output capacitance. In all other cases, no or only a limited amount of energy (due to short circuit or leakage) is consumed from the power supply. Hence by observing the supply current, one has information on the switching event and the state of the logic gate.

Keywords

Logic Gate Switching Event Current Mode Logic Logic Style Signal Arrival Time 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    D. Suzuki, M. Saeki, T. Ichikawa, “Random Switching Logic: A Countermeasure against DPA based on Transition Probability,” Cryptology ePrint Archive, report 2004/346, 2004.Google Scholar
  2. 2.
    T. Popp, S. Mangard, “Masked Dual-Rail Pre-charge Logic: DPA Resistance without the Routing Constraints,” Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems, LNCS 3659, p. 172–186, August 2005.Google Scholar
  3. 3.
    Z. Chen, Y. Zhou, “Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage,” Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems, LNCS 4249, p. 242–254, October 2006.Google Scholar
  4. 4.
    P. Schaumont, and K. Tiri, “Masking and Dual-Rail Logic don’t Add up”, Workshop on Cryptographic Hardware and Embedded Systems, September 2007.Google Scholar
  5. 5.
    E. Oswald, S. Mangard, C. Herbst, S. Tillich “Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers” CT-RSA, pp. 192–207, 2006.Google Scholar
  6. 6.
    T. Popp, M. Kirschbaum, T. Zefferer, S. Mangard “Evaluation of the Masked Logic Style MDPL on a Prototype Chip” Workshop on Cryptographic Hardware and Embedded Systems, September 2007.Google Scholar
  7. 7.
    K. Tiri, I. Verbauwhede, “A Dynamic and Differential CMOS Logic Style to Resist Power and Timing Attacks on Security IC’s”, IACR eprint archive, report 2004/066, 2004.Google Scholar
  8. 8.
    Z. T. Deniz, Y. Leblebici, “Low-Power Current Mode Logic for Improved DPA-Resistance in Embedded Systems”, International Symposium on Circuits and Systems, pp. 1059–1062, May 2005:Google Scholar
  9. 9.
    I. Hassoune, F. Mace, D. Flandre, J.-D. Legat, “Low-Swing Current Mode Logic (LSCML): A New Logic Style for Secure and Robust Smart Cards against Power Analysis Attacks”, Microelectronics Journal, vol. 37, pp. 997–1006, May 2006.CrossRefGoogle Scholar
  10. 10.
    S. Moore, R. Anderson, R. Mullins, G. Taylor “Balanced Selfchecking Asynchronous Logic for Smart Card Applications,” Journal of Microprocessors Microsystems, vol. 27.9, pp. 421–430, 2003.CrossRefGoogle Scholar
  11. 11.
    K. Kulikowski, A. Smirnov, A. Taubin “Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks” Workshop on Cryptographic Hardware and Embedded Systems, LNCS, pp. 399–413, 2006.Google Scholar
  12. 12.
    G. Bouesse, M. Renaudin, S. Dumont, F. Germain, “DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement” DATE 2005, pp. 424–429.Google Scholar
  13. 13.
    K. J. Kulikowski, M. Su, A. B. Smirnov, A. Taubin, M. G. Karpovsky, D. MacDonald, “Delay Insensitive Encoding and Power Analysis: A Balancing Act” ASYNC 2005, pp. 116–125.Google Scholar
  14. 14.
    K. J. Kulikowski, M. G. Karpovsky, A. Taubin “Power Attacks on Secure Hardware Based on Early Propagation of Data” International On-Line Testing Symposium, pp. 131–138, 2006.Google Scholar
  15. 15.
    K. Tiri, M. Akmal, and I. Verbauwhede, “A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards”, European Solid-State Circuits Conference, pp. 403–406, September 2002.Google Scholar
  16. 16.
    F. Mace, F.-X. Standaert, I. Hassoune, J.-J. Quisquater, J.-D. Legat, “A Dynamic Current Mode Logic to Counteract Power Analysis Attacks”, Conference on Design of Circuits and Integrated Systems, pp. 186–191, November 2004Google Scholar
  17. 17.
    K. Tiri, and I. Verbauwhede, “A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation”, Design, Automation and Test in Europe Conference, pp. 246–251, February 2004.Google Scholar
  18. 18.
    K. Tiri, and I. Verbauwhede, “Place and Route for Secure Standard Cell Design”, International Conference on Smart Card Research and Advanced Applications, pp. 143–158, August 2004.Google Scholar
  19. 19.
    K. Tiri, and I. Verbauwhede, “A Digital Design Flow for Secure Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1197–1208, July 2006.CrossRefGoogle Scholar
  20. 20.
    K. Tiri, D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede, “Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment”, Workshop on Cryptographic Hardware and Embedded Systems, LNCS, vol. 3659, pp. 354–365, August 2005.Google Scholar
  21. 21.
    H. Li, A. Markettos, S. Moore “Security Evaluation Against Electromagnetic Analysis at Design Time” Workshop on Cryptographic Hardware and Embedded Systems, pp. 280–292, 2005.Google Scholar
  22. 22.
    K. Tiri, and I. Verbauwhede, “Simulation Models for Side-Channel Information Leaks”, Design Automation Conference, pp. 228–233, June 2005.Google Scholar
  23. 23.
    P. Kocher, R. Lee, G. McGraw, A. Raghunathan, S. Ravi “Security as a New Dimension in Embedded System Design” Design Automation Conference, pp.735–760, 2004.Google Scholar
  24. 24.
    D. Hwang, P. Schaumont, K. Tiri, and I. Verbauwhede, “Securing Embedded Systems”, IEEE Security & Privacy Magazine, vol.4, no. 2, pp. 40–49, April 2006.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Work done while at University of CaliforniaLos AngelesUSA

Personalised recommendations