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Frequency and Voltage Scaling Design

Scaling the supply voltage of CMOS is possible over a technology-specific range; gate delays, setup and hold times and even memory access times scale monotonically with reduced operating voltage over a limited range. Linear voltage reduction results in a square-law reduction in both dynamic power consumption and in leakage power.

Keywords

Supply Voltage Clock Frequency Leakage Power Dynamic Voltage Performance Monitor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Synopsys, Inc. & ARM Limited 2007

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