The previous chapters have discussed low power design from the perspective of the system architect and chip designer. This chapter describes low power design from the perspective of the engineers who design complex IP, such as processors, DSPs, USB, PCI Express, and bus infrastructure. Until now, we have assumed that the IP is relatively fixed, and that we must add low power capability to it. Now we discuss how to design complex IP to meet our low power objectives.
KeywordsSwitching Fabric Power Controller Dynamic Voltage Scaling Clock Domain Digital Core
Unable to display preview. Download preview PDF.