Advertisement

IP Design for Low Power

The previous chapters have discussed low power design from the perspective of the system architect and chip designer. This chapter describes low power design from the perspective of the engineers who design complex IP, such as processors, DSPs, USB, PCI Express, and bus infrastructure. Until now, we have assumed that the IP is relatively fixed, and that we must add low power capability to it. Now we discuss how to design complex IP to meet our low power objectives.

Keywords

Switching Fabric Power Controller Dynamic Voltage Scaling Clock Domain Digital Core 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Synopsys, Inc. & ARM Limited 2007

Personalised recommendations