Skip to main content

FPGA and ASIC Implementations of AES

  • Chapter

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   219.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   279.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   279.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. FIPS 197: Advanced Encryption Standard. National Institute of Standards and Technology, 2001, available at http://csrc.nist.gov/publications/ fips/fips197/fips-197.pdf

  2. Amphion. Documentation of cryptographic cores, available at http://www. amphion.com

  3. D. Canright. A very compact Rijndael S-box. Technical Report NPS-MA-05-001, 2005.

    Google Scholar 

  4. D. Canright. A very compact S-box for AES. In J. R. Rao and B. Sunar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’05), LNCS, vol. 3659, pp. 441–455. Springer-Verlag, 2005.

    Google Scholar 

  5. P. Chodowiec. Comparison of the hardware performance of the AES candidates using reconfigurable hardware. Master’s thesis, George Mason University, Mar. 2002.

    Google Scholar 

  6. P. Chodowiec and K. Gaj. Very compact FPGA implementation of the AES algorithm. In Ç. K. Koç and C. Paar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’03), LNCS vol. 2779, pp. 319–333. Springer-Verlag, 2003.

    Google Scholar 

  7. J. Daemen and V. Rijmen. AES proposal: Rijndael. Technical Report, 1999, available at http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf

  8. J. Daemen and V. Rijmen. The design of Rijndael: AES - The Advanced Encryption Standard. Number ISBN 3-540-42580-2. Springer-Verlag, 2002.

    Google Scholar 

  9. A. Dandalis, V. K. Prasanna, and J. D. Rolim. A comparative study of performance of AES final candidates using FPGAs. In Ç. K. Koç and C. Paar, editors, Proc. Cryptographic Hardware and Embedded Systems Workshop (CHES’00), LNCS, vol. 1965 pp. 125–140. Springer-Verlag, 2000.

    Google Scholar 

  10. A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In Proc. Third Advanced Encryption Standard Candidate Conference (AES3), pp. 13–27. New York, USA, Apr. 13–14, 2000.

    Google Scholar 

  11. A. J. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Transactions on VLSI Systems, 9(4):545–557, 2001.

    Article  Google Scholar 

  12. V. Fischer. Realization of the round 2 candidates using Altera FPGA. Comments for The Third Advanced Encryption Standard Candidate Conference (AES3), New York, USA Apr. 13–14, 2000.

    Google Scholar 

  13. V. Fischer and M. Drutarovský. Two methods of Rijndael implementation in reconfigurable hardware. In Ç. K. Koç and C. Paar, editors, Proc. Cryptographic Hardware and Embedded Systems (CHES’01), LNCS vol. 2162, pp. 81–96. Springer-Verlag, 2001.

    Google Scholar 

  14. V. Fischer, M. Drutarovský, P. Chodowiec, and F. Gramain. InvMixColumn decomposition and multilevel resource sharing in Rijndael implementation. IEEE Transactions on VLSI Systems, 13(8):989–992, 2005.

    Article  Google Scholar 

  15. V. Fischer and F. Gramain. Resource sharing in a Rijndael implementation based on a new MixColumn and InvMixColumn relation. unpublished.

    Google Scholar 

  16. K. Gaj and P. Chodowiec. Hardware performance of the AES finalists-survey and analysis results. Technical Report, George Mason University, 2000, available at http://ece.gmu.edu/crypto/AES_survey.pdf

  17. K. Gaj and P. Chodowiec. Comparison of the hardware performance of the AES candidates using reconfigurable hardware. In Proc. Third Advanced Encryption Standard Candidate Conference (AES3), pp. 40–54. New York, USA, Apr. 13–14, 2000.

    Google Scholar 

  18. K. Gaj and P. Chodowiec. Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays. In Proc. The Cryptographer’s Track at the RSA Security Conference (CT-RSA’01), LNCS vol. 2020, pp. 84–99. Springer-Verlag, 2001.

    Google Scholar 

  19. T. Good and M. Benaissa. AES FPGA from the fastest to the smallest. In J. R. Rao and B. Sunar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’05), LNCS, vol. 3659, pp. 427–440. Springer-Verlag, 2005.

    Google Scholar 

  20. Helion. Documentation of cryptographic cores. Available at http://www.heliontech.com

  21. T. Ichikawa, T. Kasuya, and M. Matsui. Hardware evaluation of the AES finalists. In Proc. Third Advanced Encryption Standard Candidate Conference (AES3), pp. 279–285. New York, USA, Apr. 13–14, 2000.

    Google Scholar 

  22. K. U. Järvinen, M. T. Tommiska, and J. O. Skyttä. A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In Proc. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2003), pp. 207–215. Monterey, CA, Feb. 23–25, 2003.

    Google Scholar 

  23. H. Kuo and I. Verbauwhede. Architectural optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael algorithm. In Ç. K. Koç and C. Paar, editors, Proc. Cryptographic Hardware and Embedded Systems (CHES’01), LNCS, vol. 2162, pp. 51–64. Springer-Verlag, 2001.

    Google Scholar 

  24. I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. IEEE Trans. Computer-Aided Design, 62(2), Feb. 2007.

    Google Scholar 

  25. A. Lutz, J. Treichler, F. Gürkaynak, H. Kaeslin, G. Basler, A. Erni, S. Reichmuth, P. Rommens, S. Oetiker, and W. Fichtner. 2Gbit/s hardware realizations of RIJNDAEL and SERPENT: A comparative analysis. In Ç. K. Koç and C. Paar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’02), LNCS, vol. 2523, pp. 144–158. Springer-Verlag, 2002.

    Google Scholar 

  26. U. Mayer, C. Oelsner, and T. Köhler. Evaluation of different Rijndael implementations for high end servers. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2002), vol. 2, pp. 348–351. Scottsdale, Arizona, USA 2002.

    Google Scholar 

  27. S. McMillan and C. Patterson. JBits implementations of the Advanced Encryption Standard (Rijndael). In Proc. Field-Programmable Logic and Applications (FPL’01), LNCS, vol. 2147, pp. 162–171. Springer-Verlag, 2001.

    Google Scholar 

  28. N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede. A systematic evaluation of compact hardware implementations for the Rijndael S-box. In J. R. Rao and B. Sunar, editors, Proc. (CT-RSA’05), LNCS, vol. 3376, pp. 323–333. Springer-Verlag, 2005.

    Google Scholar 

  29. S. Morioka and A. Satoh. A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture. In Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 98–103. Freiburg, Germany, 2002.

    Google Scholar 

  30. S. Morioka and A. Satoh. An optimized S-Box circuit architecture for low power AES design. In Ç. K. Koç and C. Paar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’02), LNCS, vol. 2523, pp. 172–186. Springer-Verlag, 2002.

    Google Scholar 

  31. A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. Rao, and P. Rohatgi. Efficient Rijndael encryption implementation with composite field arithmetic. In Ç. K. Koç and C. Paar, editors, Proc. Cryptographic Hardware and Embedded Systems (CHES’01), LNCS, vol. 2162, pp. 171–184. Springer-Verlag, 2001.

    Google Scholar 

  32. G. Saggese, A. Mazzeo, N. Mazzocca, and A. Strollo. An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In Proc. International Conference on Field-Programmable Logic and Applications (FPL’03), LNCS, vol. 2778, pp. 292–302. Springer-Verlag, 2003.

    Google Scholar 

  33. A. Satoh, S. Morioka, K. Takano, and S. Munetoh. A compact Rijndael hardware architecture with S-Box optimization. In Proc. Theory and Application of Cryptology and Information Security (ASIACRYPT’01), LNCS, vol. 2248, pp. 239–254. Springer-Verlag, 2001.

    Google Scholar 

  34. P. R. Schaumont, H. Kuo, and I. M. Verbauwhede. Unlocking the design secrets of a 2.29 Gb/s Rijndael processor. In Proc. ACM Conference on Design Automation (DAC 2002), pages 634–639. New Orleans, Louisiana, USA, 2002.

    Google Scholar 

  35. N. Sklavos and O. Koufopavlou. Architectures and VLSI implementations of the AES-Proposal Rijndael. IEEE Transactions on Computers, 51(12): 1454–1459, 2002.

    Article  MathSciNet  Google Scholar 

  36. F.-X. Standaert, G. Rouvroy, J.-J. Quisquater, and J.-D. Legat. Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs. In Ç. K. Koç and C. Paar, editors, Proc. International Workshop on Cryptographic Hardware and Embedded Systems (CHES’03), LNCS, vol. 2779, pp. 334–350. Springer-Verlag, 2003.

    Google Scholar 

  37. K. Tiri, D. Hwang, A. Hodjat, B. Lai, S. Yang, P. Schaumont, and I. Verbauwhede. Prototype IC with WDDL and differential routing - DPA resistance assessment. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems – CHES 2005, LNCS, vol. 3659, pp. 354–365. Springer-Verlag, 2005.

    Google Scholar 

  38. K. Tiri and I. Verbauwhede. Securing encryption algorithms against dpa at the logic level: next generation smart card technology. In Ç. K. Koç, C. Paar, and C. D. Walter, editors, Cryptographic Hardware and Embedded Systems - CHES 2003, LNCS, vol. 2779, pp. 125–136, Cologne, Germany, 2003. Springer-Verlag.

    Google Scholar 

  39. K. Tiri and I. Verbauwhede. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In Proc. of Design Automation and Test in Europe (DATE 2004), pp. 246–251. Paris, France, 2004.

    Google Scholar 

  40. K. Tiri and I. Verbauwhede. A VLSI design flow for secure side-channel attack resistant ICs. In Proc. of Design Automation and Test in Europe (DATE 2005), pp. 58–63, 2005.

    Google Scholar 

  41. I. Verbauwhede, P. Schaumont, and H. Kuo. Design and performance testing of a 2.29-GB/s Rijndael processor. IEEE Journal of Solid-State Circuits, 38(3):569–572, 2003.

    Article  Google Scholar 

  42. B. Weeks, M. Bean, T. Rozylowicz, and C. Ficke. Hardware performance simulations of Round 2 Advanced Encryption Standard algorithms. In Proc. Third Advanced Encryption Standard Candidate Conference (AES3). New York, USA, Apr. 13–14, 2000.

    Google Scholar 

  43. J. Wolkerstorfer. An ASIC implementation of the AES MixColumn operation. In Proc. Austrochip 2001, pp. 129–132. Vienna, Austria, Oct. 12, 2001.

    Google Scholar 

  44. J. Wolkerstorfer, E. Oswald, and M. Lamberger. An ASIC implementation of the AES SBoxes. In Proc. The Cryptographer’s Track at the RSA Security Conference (CT-RSA 2002), LNCS, vol. 2271, pp. 67–78. Springer-Verlag, 2002.

    Google Scholar 

  45. A. C. Zigiotto and R. d’Amore. A low-cost FPGA implementation of the Advanced Encryption Standard algorithm. In Proc. Symposium on Integrated Circuits and Systems Design (SBCCI’02), pp. 191–196. Porto Alegre, Brazil, 2002.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Kris Gaj .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Gaj, K., Chodowiec, P. (2009). FPGA and ASIC Implementations of AES. In: Koç, Ç.K. (eds) Cryptographic Engineering. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-71817-0_10

Download citation

  • DOI: https://doi.org/10.1007/978-0-387-71817-0_10

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-71816-3

  • Online ISBN: 978-0-387-71817-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics