Efficient Structures for PLL’s Loop Filter Design in FPGAs in High-Datarate Wireless Receivers – Theory and Case Study

  • Yair Linn
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 44)


In most contemporary phase lock loops (PLLs) used in high-datarate wireless receivers, some or all of the PLL’s components are implemented digitally, in particular the PLL’s loop filter. In this chapter we develop the theory behind new efficient structures for the implementation of loop filters within FPGAs (Field Programmable Gate Arrays) using fixed-point arithmetic. The theory is then investigated via a case study, in which we present FPGA hardware mapping results that show that employing the proposed method results in a decrease of more than 70% in the logic gate count needed as compared to the conventional implementation.


State Machine Phase Noise Clock Cycle Critical Path Partial Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The author gratefully acknowledges the financial support provided by NSERC (National Sciences and Engineering Research Council of Canada) through its Canadian Graduate Scholarship.


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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Universidad Pontificia BolivarianaBucaramangaColombia

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