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Efficient Structures for PLL’s Loop Filter Design in FPGAs in High-Datarate Wireless Receivers – Theory and Case Study

Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 44)

Abstract

In most contemporary phase lock loops (PLLs) used in high-datarate wireless receivers, some or all of the PLL’s components are implemented digitally, in particular the PLL’s loop filter. In this chapter we develop the theory behind new efficient structures for the implementation of loop filters within FPGAs (Field Programmable Gate Arrays) using fixed-point arithmetic. The theory is then investigated via a case study, in which we present FPGA hardware mapping results that show that employing the proposed method results in a decrease of more than 70% in the logic gate count needed as compared to the conventional implementation.

Keywords

State Machine Phase Noise Clock Cycle Critical Path Partial Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgment

The author gratefully acknowledges the financial support provided by NSERC (National Sciences and Engineering Research Council of Canada) through its Canadian Graduate Scholarship.

References

  1. 1.
    H. Meyr, M. Moeneclaey, and S. Fechtel, Digital communication receivers: synchronization, channel estimation, and signal processing. NY: Wiley, 1998.Google Scholar
  2. 2.
    U. Mengali and A. N. DAndrea, Synchronization techniques for digital receivers. NY: Plenum Press, 1997.Google Scholar
  3. 3.
    H. Meyr and G. Ascheid, Synchronization in digital communications. NY: Wiley, 1990.Google Scholar
  4. 4.
    F. M. Gardner, Phaselock techniques, 2nd ed. NY: Wiley, 1979.Google Scholar
  5. 5.
    R. E. Best, Phase-locked loops: theory, design, and applications, 2nd ed. NY: McGraw-Hill, 1993.Google Scholar
  6. 6.
    W. P. Robins, Phase noise in signal sources. (Theory and applications). London: Peter Peregrinus, 1982.Google Scholar
  7. 7.
    ETSI (European Telecommunications Standards Institute), “DVB-S2 Technical Report ETSI TR 102 376 V1.1.1,” 2005.Google Scholar
  8. 8.
    Y. Linn, “A Methodical Approach to Hybrid PLL Design for High-Speed Wireless Communications,” in Proc. 8th IEEE Wireless and Microwave Technology Conf. (WAMICON 2006), Clearwater, FL, Dec. 4–5, 2006.Google Scholar
  9. 9.
    Y. Linn, “A Tutorial on Hybrid PLL Design for Synchronization in Wireless Receivers,” in Proc. International Seminar: 15 Years of Electronic Engineering, Universidad Pontificia Bolivariana, Bucaramanga, Colombia, Aug. 15–19, 2006 (invited paper).Google Scholar
  10. 10.
    Y. Linn, “Synchronization and Receiver Structures in Digital Wireless Communications (workshop notes),” in International Seminar: 15 Years of Electronic Engineering. Universidad Pontificia Bolivariana, Bucaramanga, Colombia, Aug. 15–19, 2006.Google Scholar
  11. 11.
    A. Blanchard, Phase-locked loops. Application to coherent receiver design. NY: Wiley, 1976.Google Scholar
  12. 12.
    J. J. D'Azzo and C. H. Houpis, Linear control system analysis and design: conventional and modern, 3rd ed. NY: McGraw-Hill, 1988.Google Scholar
  13. 13.
    A. V. Oppenheim and R. W. Schafer, Discrete-time signal processing. NJ: Prentice Hall, 1989.MATHGoogle Scholar
  14. 14.
    F. M. Gardner, “Interpolation in digital modems. I. Fundamentals,” IEEE Trans. Commun., 41, 3, 501–507, Mar. 1993.CrossRefMATHGoogle Scholar
  15. 15.
    S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd ed. NY: McGraw-Hill, 2005.Google Scholar
  16. 16.
    Xilinx Inc., “Virtex Series FPGAs,” at http://www.xilinx.com/products/silicon_solutions/ fpgas/virtex/index.htm, accessed Nov. 2006

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Universidad Pontificia BolivarianaBucaramangaColombia

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